Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1224700188	190963	0	0
ctrl_regwen_rd_A	1224700188	3886	0	0
exec_rd_A	1224700188	3311	0	0
exec_regwen_rd_A	1224700188	3640	0	0
readback_rd_A	1224700188	2562	0	0
readback_regwen_rd_A	1224700188	2183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	190963	0	0
T23	186574	5678	0	0
T24	75210	3293	0	0
T25	141799	7557	0	0
T27	33551	0	0	0
T40	153916	0	0	0
T42	71929	0	0	0
T45	525204	0	0	0
T46	0	5496	0	0
T49	542944	0	0	0
T54	69402	0	0	0
T55	71111	0	0	0
T70	0	599	0	0
T71	0	1206	0	0
T72	0	165	0	0
T73	0	2288	0	0
T74	0	2141	0	0
T75	0	1431	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	3886	0	0
T28	34290	0	0	0
T44	115482	0	0	0
T47	0	235	0	0
T50	525357	0	0	0
T51	262675	0	0	0
T70	14694	61	0	0
T72	0	28	0	0
T75	0	138	0	0
T76	157815	0	0	0
T116	0	70	0	0
T117	0	125	0	0
T118	0	289	0	0
T119	0	310	0	0
T120	0	414	0	0
T121	0	138	0	0
T122	854429	0	0	0
T123	71261	0	0	0
T124	84386	0	0	0
T125	70692	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	3311	0	0
T28	34290	0	0	0
T44	115482	0	0	0
T47	0	183	0	0
T50	525357	0	0	0
T51	262675	0	0	0
T70	14694	42	0	0
T72	0	43	0	0
T75	0	90	0	0
T76	157815	0	0	0
T116	0	76	0	0
T117	0	125	0	0
T118	0	214	0	0
T119	0	290	0	0
T120	0	338	0	0
T121	0	95	0	0
T122	854429	0	0	0
T123	71261	0	0	0
T124	84386	0	0	0
T125	70692	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	3640	0	0
T28	34290	0	0	0
T44	115482	0	0	0
T47	0	118	0	0
T50	525357	0	0	0
T51	262675	0	0	0
T70	14694	28	0	0
T72	0	61	0	0
T75	0	93	0	0
T76	157815	0	0	0
T116	0	63	0	0
T117	0	139	0	0
T118	0	309	0	0
T119	0	333	0	0
T120	0	323	0	0
T121	0	144	0	0
T122	854429	0	0	0
T123	71261	0	0	0
T124	84386	0	0	0
T125	70692	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	2562	0	0
T28	34290	0	0	0
T44	115482	0	0	0
T47	0	178	0	0
T50	525357	0	0	0
T51	262675	0	0	0
T70	14694	39	0	0
T72	0	14	0	0
T75	0	132	0	0
T76	157815	0	0	0
T116	0	28	0	0
T117	0	107	0	0
T118	0	302	0	0
T119	0	376	0	0
T120	0	405	0	0
T121	0	138	0	0
T122	854429	0	0	0
T123	71261	0	0	0
T124	84386	0	0	0
T125	70692	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224700188	2183	0	0
T28	34290	0	0	0
T44	115482	0	0	0
T47	0	188	0	0
T50	525357	0	0	0
T51	262675	0	0	0
T70	14694	19	0	0
T72	0	31	0	0
T75	0	58	0	0
T76	157815	0	0	0
T116	0	37	0	0
T117	0	82	0	0
T118	0	252	0	0
T119	0	333	0	0
T120	0	309	0	0
T121	0	122	0	0
T122	854429	0	0	0
T123	71261	0	0	0
T124	84386	0	0	0
T125	70692	0	0	0