Line Coverage for Module :
tlul_adapter_sram
| Line No. | Total | Covered | Percent |
TOTAL | | 77 | 76 | 98.70 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 99 | 4 | 3 | 75.00 |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 8 | 100.00 |
ALWAYS | 299 | 6 | 6 | 100.00 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
0 |
1 |
|
|
|
MISSING_ELSE |
114 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
|
unreachable |
510 |
1 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Cond Coverage for Module :
tlul_adapter_sram
| Total | Covered | Percent |
Conditions | 119 | 103 | 86.55 |
Logical | 119 | 103 | 86.55 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T15,T16,T17 |
1 | 0 | 0 | 0 | Not Covered | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T15,T16,T17 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Covered | T15,T16,T17 |
1 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T5 |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T5 |
0 | 0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T3,T4,T6 |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T3,T6,T23 |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T23 |
1 | 1 | Covered | T3,T4,T5 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T3,T4,T5 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T40,T43,T44 |
1 | 1 | Covered | T3,T4,T5 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T5 |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Not Covered | |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Not Covered | |
1 | 0 | 1 | 1 | Not Covered | |
1 | 1 | 0 | 1 | Covered | T3,T6,T23 |
1 | 1 | 1 | 0 | Covered | T3,T6,T7 |
1 | 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T20 |
1 | 1 | Covered | T3,T4,T5 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T6,T20 |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T6,T20 |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T6,T40 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T6,T23 |
1 | 1 | 1 | Covered | T3,T6,T23 |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T6,T23 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | 1 | Covered | T3,T6,T23 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T4 |
0 | 1 | Covered | T23,T24,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T5 |
1 | 0 | 1 | Covered | T3,T6,T41 |
1 | 1 | 0 | Covered | T3,T6,T23 |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T3,T4,T5 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T23 |
1 | 1 | Covered | T3,T4,T5 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
Branch Coverage for Module :
tlul_adapter_sram
| Line No. | Total | Covered | Percent |
Branches |
|
32 |
31 |
96.88 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
2 |
100.00 |
TERNARY |
347 |
3 |
3 |
100.00 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
2 |
100.00 |
IF |
129 |
3 |
3 |
100.00 |
IF |
281 |
4 |
4 |
100.00 |
IF |
301 |
3 |
3 |
100.00 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
99 |
3 |
2 |
66.67 |
IF |
496 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T5 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T3,T6,T20 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T15,T16,T17 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T3,T6,T23 |
1 |
0 |
1 |
Covered |
T3,T4,T5 |
1 |
0 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T4,T5 |
1 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 99 if ((!rst_ni))
-2-: 101 if (readback_error)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Unreachable |
|
1 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_sram
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
92826048 |
0 |
0 |
T3 |
310834 |
92851 |
0 |
0 |
T4 |
570170 |
203478 |
0 |
0 |
T5 |
508563 |
56763 |
0 |
0 |
T6 |
107674 |
37297 |
0 |
0 |
T9 |
45279 |
5746 |
0 |
0 |
T10 |
197478 |
32768 |
0 |
0 |
T11 |
765516 |
98955 |
0 |
0 |
T12 |
131145 |
622592 |
0 |
0 |
T23 |
186574 |
1333 |
0 |
0 |
T40 |
153916 |
103056 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
92826048 |
0 |
0 |
T3 |
310834 |
92851 |
0 |
0 |
T4 |
570170 |
203478 |
0 |
0 |
T5 |
508563 |
56763 |
0 |
0 |
T6 |
107674 |
37297 |
0 |
0 |
T9 |
45279 |
5746 |
0 |
0 |
T10 |
197478 |
32768 |
0 |
0 |
T11 |
765516 |
98955 |
0 |
0 |
T12 |
131145 |
622592 |
0 |
0 |
T23 |
186574 |
1333 |
0 |
0 |
T40 |
153916 |
103056 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul_adapter_sram
| Line No. | Total | Covered | Percent |
TOTAL | | 77 | 76 | 98.70 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 99 | 4 | 3 | 75.00 |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
ALWAYS | 129 | 4 | 4 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 151 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
CONT_ASSIGN | 272 | 1 | 1 | 100.00 |
CONT_ASSIGN | 273 | 1 | 1 | 100.00 |
CONT_ASSIGN | 274 | 1 | 1 | 100.00 |
ALWAYS | 279 | 8 | 8 | 100.00 |
ALWAYS | 299 | 6 | 6 | 100.00 |
CONT_ASSIGN | 313 | 1 | 1 | 100.00 |
CONT_ASSIGN | 317 | 1 | 1 | 100.00 |
CONT_ASSIGN | 336 | 1 | 1 | 100.00 |
CONT_ASSIGN | 341 | 1 | 1 | 100.00 |
CONT_ASSIGN | 347 | 1 | 1 | 100.00 |
CONT_ASSIGN | 359 | 1 | 1 | 100.00 |
ALWAYS | 362 | 3 | 3 | 100.00 |
CONT_ASSIGN | 369 | 1 | 1 | 100.00 |
CONT_ASSIGN | 390 | 1 | 1 | 100.00 |
CONT_ASSIGN | 391 | 1 | 1 | 100.00 |
CONT_ASSIGN | 392 | 1 | 1 | 100.00 |
CONT_ASSIGN | 393 | 1 | 1 | 100.00 |
ALWAYS | 423 | 6 | 6 | 100.00 |
ALWAYS | 435 | 5 | 5 | 100.00 |
CONT_ASSIGN | 446 | 1 | 1 | 100.00 |
CONT_ASSIGN | 447 | 1 | 1 | 100.00 |
CONT_ASSIGN | 456 | 1 | 1 | 100.00 |
CONT_ASSIGN | 457 | 1 | 1 | 100.00 |
CONT_ASSIGN | 459 | 1 | 1 | 100.00 |
CONT_ASSIGN | 460 | 1 | 1 | 100.00 |
CONT_ASSIGN | 467 | 1 | 1 | 100.00 |
CONT_ASSIGN | 470 | 1 | 1 | 100.00 |
CONT_ASSIGN | 474 | 1 | 1 | 100.00 |
CONT_ASSIGN | 475 | 1 | 1 | 100.00 |
CONT_ASSIGN | 477 | 1 | 1 | 100.00 |
CONT_ASSIGN | 479 | 1 | 1 | 100.00 |
CONT_ASSIGN | 486 | 1 | 1 | 100.00 |
ALWAYS | 492 | 4 | 4 | 100.00 |
CONT_ASSIGN | 526 | 1 | 1 | 100.00 |
CONT_ASSIGN | 531 | 1 | 1 | 100.00 |
CONT_ASSIGN | 536 | 0 | 0 | |
CONT_ASSIGN | 620 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
101 |
1 |
1 |
102 |
0 |
1 |
|
|
|
MISSING_ELSE |
114 |
1 |
1 |
129 |
1 |
1 |
130 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
|
|
|
MISSING_ELSE |
138 |
1 |
1 |
144 |
1 |
1 |
151 |
1 |
1 |
176 |
1 |
1 |
188 |
1 |
1 |
272 |
1 |
1 |
273 |
1 |
1 |
274 |
1 |
1 |
279 |
1 |
1 |
281 |
1 |
1 |
282 |
1 |
1 |
284 |
1 |
1 |
285 |
1 |
1 |
286 |
1 |
1 |
289 |
1 |
1 |
292 |
1 |
1 |
299 |
1 |
1 |
301 |
1 |
1 |
302 |
1 |
1 |
303 |
1 |
1 |
305 |
1 |
1 |
308 |
1 |
1 |
313 |
1 |
1 |
317 |
1 |
1 |
336 |
1 |
1 |
341 |
1 |
1 |
347 |
1 |
1 |
359 |
1 |
1 |
362 |
1 |
1 |
363 |
1 |
1 |
365 |
1 |
1 |
369 |
1 |
1 |
390 |
1 |
1 |
391 |
1 |
1 |
392 |
1 |
1 |
393 |
1 |
1 |
423 |
1 |
1 |
424 |
1 |
1 |
426 |
1 |
1 |
427 |
1 |
1 |
428 |
1 |
1 |
429 |
1 |
1 |
|
|
|
MISSING_ELSE |
435 |
1 |
1 |
436 |
1 |
1 |
438 |
1 |
1 |
439 |
1 |
1 |
440 |
1 |
1 |
|
|
|
MISSING_ELSE |
446 |
1 |
1 |
447 |
1 |
1 |
456 |
1 |
1 |
457 |
1 |
1 |
459 |
1 |
1 |
460 |
1 |
1 |
467 |
1 |
1 |
470 |
1 |
1 |
474 |
1 |
1 |
475 |
1 |
1 |
477 |
1 |
1 |
479 |
1 |
1 |
486 |
1 |
1 |
492 |
1 |
1 |
496 |
1 |
1 |
498 |
1 |
1 |
504 |
|
unreachable |
510 |
1 |
1 |
|
|
|
MISSING_ELSE |
526 |
1 |
1 |
531 |
1 |
1 |
536 |
|
unreachable |
620 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram
| Total | Covered | Percent |
Conditions | 114 | 102 | 89.47 |
Logical | 114 | 102 | 89.47 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 114
EXPRESSION (readback_error | readback_error_q)
-------1------ --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
LINE 131
EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
-----1---- -------2------ --------3-------- ------4------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 1 | 0 | Not Covered | |
0 | 1 | 0 | 0 | Covered | T15,T16,T17 |
1 | 0 | 0 | 0 | Not Covered | |
LINE 138
EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
-----1---- -------2------ --------3-------- ------4------ ------5-----
-1- | -2- | -3- | -4- | -5- | Status | Tests |
0 | 0 | 0 | 0 | 0 | Covered | T1,T2,T3 |
0 | 0 | 0 | 0 | 1 | Covered | T15,T16,T17 |
0 | 0 | 0 | 1 | 0 | Not Covered | |
0 | 0 | 1 | 0 | 0 | Not Covered | |
0 | 1 | 0 | 0 | 0 | Covered | T15,T16,T17 |
1 | 0 | 0 | 0 | 0 | Not Covered | |
LINE 144
EXPRESSION
Number Term
1 ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? (((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0)) : 1'b0)
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
---------------1-------------- ----------------2----------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T5 |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 144
SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
----------------1----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 176
EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
------1------ ------2----- ------3----- -----4----- -----5---- -----6----
-1- | -2- | -3- | -4- | -5- | -6- | Status | Tests | Exclude Annotation |
0 | 0 | 0 | 0 | 0 | 0 | Covered | T3,T4,T5 |
0 | 0 | 0 | 0 | 0 | 1 | Not Covered | |
0 | 0 | 0 | 0 | 1 | 0 | Covered | T3,T4,T6 |
0 | 0 | 0 | 1 | 0 | 0 | Covered | T3,T6,T23 |
0 | 0 | 1 | 0 | 0 | 0 | Unreachable | |
0 | 1 | 0 | 0 | 0 | 0 | Unreachable | |
1 | 0 | 0 | 0 | 0 | 0 | Excluded | |
VC_COV_UNR |
LINE 272
EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T23 |
1 | 1 | Covered | T3,T4,T5 |
LINE 273
EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
--------1------- --------2-------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T6 |
1 | 1 | Covered | T3,T4,T5 |
LINE 274
EXPRESSION (req_o & gnt_i)
--1-- --2--
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Excluded | T1,T2,T3 |
VC_COV_UNR |
1 | 0 | Covered | T40,T43,T44 |
1 | 1 | Covered | T3,T4,T5 |
LINE 285
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 302
EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 303
EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
---------1--------- ---------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T3,T4,T5 |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Not Covered | |
LINE 313
EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
---1--- -------2------ -------3------ --------------4-------------
-1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
0 | 1 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 0 | 1 | 1 | Excluded | |
VC_COV_UNR |
1 | 1 | 0 | 1 | Covered | T3,T6,T23 |
1 | 1 | 1 | 0 | Covered | T3,T6,T7 |
1 | 1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 313
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 341
EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
-------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 341
SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T20 |
1 | 1 | Covered | T3,T4,T5 |
LINE 347
EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
-----------------1-----------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T6,T20 |
LINE 347
SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
-----1---- ---------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T6,T20 |
LINE 347
SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
-----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 359
EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
-------1------ --------2------- ----------3----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T6,T40 |
1 | 0 | 1 | Covered | T1,T2,T3 |
1 | 1 | 0 | Covered | T3,T6,T23 |
1 | 1 | 1 | Covered | T3,T6,T23 |
LINE 369
EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
--------------------1--------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
---1--- --------------2-------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 369
SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
---1---
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 369
EXPRESSION (d_valid && d_error)
---1--- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T6,T23 |
LINE 369
EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
-------------1------------ -------2------ ---------3-------- -----------4----------
-1- | -2- | -3- | -4- | Status | Tests |
0 | 1 | 1 | 1 | Covered | T2,T3,T4 |
1 | 0 | 1 | 1 | Covered | T3,T6,T23 |
1 | 1 | 0 | 1 | Not Covered | |
1 | 1 | 1 | 0 | Unreachable | |
1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 369
SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
--1-- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T2,T3,T4 |
0 | 1 | Covered | T23,T24,T25 |
1 | 0 | Covered | T1,T2,T3 |
LINE 390
EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
--------1------- -------2------ ---------3---------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T3,T4,T5 |
1 | 0 | 1 | Covered | T3,T6,T41 |
1 | 1 | 0 | Covered | T3,T6,T23 |
1 | 1 | 1 | Covered | T3,T4,T5 |
LINE 392
EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
--------1------- ----------------------------2---------------------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 393
EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
--------1-------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 429
EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T3,T4,T5 |
LINE 429
SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
---------1-------- --2-
-1- | -2- | Status | Tests |
0 | 1 | Covered | T3,T6,T23 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 460
EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
-------------1------------
-1- | Status | Tests |
0 | Covered | T3,T4,T5 |
1 | Covered | T1,T2,T3 |
LINE 460
SUB-EXPRESSION (tl_i_int.a_opcode != Get)
-------------1------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 474
EXPRESSION (sram_ack & ((~we_o)))
----1--- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 477
EXPRESSION (rvalid_i & reqfifo_rvalid)
----1--- -------2------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T3,T4,T5 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T3,T4,T5 |
LINE 531
EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
LINE 531
SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
--------------1------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T6,T23 |
1 | 1 | Covered | T3,T4,T5 |
LINE 531
SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
--------------1-------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T3,T4,T5 |
Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram
| Line No. | Total | Covered | Percent |
Branches |
|
32 |
31 |
96.88 |
TERNARY |
144 |
2 |
2 |
100.00 |
TERNARY |
341 |
2 |
2 |
100.00 |
TERNARY |
347 |
3 |
3 |
100.00 |
TERNARY |
393 |
2 |
2 |
100.00 |
TERNARY |
531 |
2 |
2 |
100.00 |
IF |
129 |
3 |
3 |
100.00 |
IF |
281 |
4 |
4 |
100.00 |
IF |
301 |
3 |
3 |
100.00 |
IF |
362 |
2 |
2 |
100.00 |
IF |
426 |
2 |
2 |
100.00 |
IF |
438 |
2 |
2 |
100.00 |
IF |
99 |
3 |
2 |
66.67 |
IF |
496 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T3,T4,T5 |
LineNo. Expression
-1-: 341 ((vld_rd_rsp & (~d_error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ?
-2-: 347 (vld_rd_rsp) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T3,T6,T20 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 393 (tl_i_int.a_valid) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 129 if ((!rst_ni))
-2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T15,T16,T17 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 281 if (reqfifo_rvalid)
-2-: 282 if (reqfifo_rdata.error)
-3-: 285 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
1 |
- |
Covered |
T3,T6,T23 |
1 |
0 |
1 |
Covered |
T3,T4,T5 |
1 |
0 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 301 if (reqfifo_rvalid)
-2-: 302 if ((reqfifo_rdata.op == OpRead))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T3,T4,T5 |
1 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 362 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 426 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 438 if (tl_i_int.a_valid)
Branches:
-1- | Status | Tests |
1 |
Covered |
T3,T4,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 99 if ((!rst_ni))
-2-: 101 if (readback_error)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 496 if ((|sramreqfifo_rdata.mask))
-2-: 498 if (DataXorAddr)
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Unreachable |
|
1 |
0 |
Covered |
T3,T4,T5 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram
Assertion Details
AddrOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
DataIntgOptions_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
ReqOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
SramDwHasByteGranularity_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
SramDwIsMultipleOfTlulWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
TlOutKnownIfFifoKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
TlOutValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WdataOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WeOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
WmaskOutKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
1212872019 |
0 |
0 |
T1 |
1369 |
1319 |
0 |
0 |
T2 |
33588 |
33504 |
0 |
0 |
T3 |
310834 |
310794 |
0 |
0 |
T4 |
570170 |
570120 |
0 |
0 |
T5 |
508563 |
508508 |
0 |
0 |
T6 |
107674 |
107667 |
0 |
0 |
T9 |
45279 |
45202 |
0 |
0 |
T10 |
197478 |
197412 |
0 |
0 |
T11 |
765516 |
765441 |
0 |
0 |
T12 |
131145 |
131144 |
0 |
0 |
adapterNoReadOrWrite
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
897 |
897 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
rvalidHighReqFifoEmpty
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
92826048 |
0 |
0 |
T3 |
310834 |
92851 |
0 |
0 |
T4 |
570170 |
203478 |
0 |
0 |
T5 |
508563 |
56763 |
0 |
0 |
T6 |
107674 |
37297 |
0 |
0 |
T9 |
45279 |
5746 |
0 |
0 |
T10 |
197478 |
32768 |
0 |
0 |
T11 |
765516 |
98955 |
0 |
0 |
T12 |
131145 |
622592 |
0 |
0 |
T23 |
186574 |
1333 |
0 |
0 |
T40 |
153916 |
103056 |
0 |
0 |
rvalidHighWhenRspFifoFull
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1212974813 |
92826048 |
0 |
0 |
T3 |
310834 |
92851 |
0 |
0 |
T4 |
570170 |
203478 |
0 |
0 |
T5 |
508563 |
56763 |
0 |
0 |
T6 |
107674 |
37297 |
0 |
0 |
T9 |
45279 |
5746 |
0 |
0 |
T10 |
197478 |
32768 |
0 |
0 |
T11 |
765516 |
98955 |
0 |
0 |
T12 |
131145 |
622592 |
0 |
0 |
T23 |
186574 |
1333 |
0 |
0 |
T40 |
153916 |
103056 |
0 |
0 |