| T795 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1286685579 |
|
|
Jul 26 07:07:09 PM PDT 24 |
Jul 26 07:09:16 PM PDT 24 |
1999365319 ps |
| T796 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.178057306 |
|
|
Jul 26 07:06:36 PM PDT 24 |
Jul 26 07:17:27 PM PDT 24 |
5256695248 ps |
| T797 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.1273626762 |
|
|
Jul 26 07:05:42 PM PDT 24 |
Jul 26 07:05:49 PM PDT 24 |
2820499117 ps |
| T798 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.3115409099 |
|
|
Jul 26 07:04:47 PM PDT 24 |
Jul 26 07:04:56 PM PDT 24 |
254675751 ps |
| T799 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3367690696 |
|
|
Jul 26 07:05:26 PM PDT 24 |
Jul 26 07:10:54 PM PDT 24 |
3802991077 ps |
| T800 |
/workspace/coverage/default/40.sram_ctrl_regwen.1229126457 |
|
|
Jul 26 07:06:15 PM PDT 24 |
Jul 26 07:11:01 PM PDT 24 |
4977040164 ps |
| T801 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.582944719 |
|
|
Jul 26 07:03:07 PM PDT 24 |
Jul 26 07:05:13 PM PDT 24 |
2507065010 ps |
| T802 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.2958134156 |
|
|
Jul 26 07:03:19 PM PDT 24 |
Jul 26 07:27:57 PM PDT 24 |
32662571968 ps |
| T803 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.99046649 |
|
|
Jul 26 07:02:46 PM PDT 24 |
Jul 26 07:02:50 PM PDT 24 |
1351323582 ps |
| T804 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2202545159 |
|
|
Jul 26 07:03:47 PM PDT 24 |
Jul 26 07:03:50 PM PDT 24 |
680874078 ps |
| T805 |
/workspace/coverage/default/8.sram_ctrl_bijection.430932064 |
|
|
Jul 26 07:02:49 PM PDT 24 |
Jul 26 07:50:01 PM PDT 24 |
479145646989 ps |
| T806 |
/workspace/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.3135218011 |
|
|
Jul 26 07:02:46 PM PDT 24 |
Jul 26 07:03:17 PM PDT 24 |
2094575282 ps |
| T807 |
/workspace/coverage/default/44.sram_ctrl_partial_access_b2b.392807281 |
|
|
Jul 26 07:07:06 PM PDT 24 |
Jul 26 07:13:04 PM PDT 24 |
198603116955 ps |
| T808 |
/workspace/coverage/default/6.sram_ctrl_multiple_keys.3608852565 |
|
|
Jul 26 07:02:51 PM PDT 24 |
Jul 26 07:16:39 PM PDT 24 |
17166663024 ps |
| T809 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.319844499 |
|
|
Jul 26 07:03:01 PM PDT 24 |
Jul 26 07:04:04 PM PDT 24 |
1010667828 ps |
| T810 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.559057083 |
|
|
Jul 26 07:03:04 PM PDT 24 |
Jul 26 07:15:36 PM PDT 24 |
7197181332 ps |
| T811 |
/workspace/coverage/default/32.sram_ctrl_throughput_w_partial_write.1637126712 |
|
|
Jul 26 07:04:46 PM PDT 24 |
Jul 26 07:07:25 PM PDT 24 |
3005931107 ps |
| T812 |
/workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.1549250664 |
|
|
Jul 26 07:04:03 PM PDT 24 |
Jul 26 07:07:38 PM PDT 24 |
8336643038 ps |
| T813 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.3420065968 |
|
|
Jul 26 07:07:56 PM PDT 24 |
Jul 26 07:07:59 PM PDT 24 |
495186925 ps |
| T814 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.779191423 |
|
|
Jul 26 07:03:13 PM PDT 24 |
Jul 26 07:03:21 PM PDT 24 |
2822654289 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.3603837327 |
|
|
Jul 26 07:03:08 PM PDT 24 |
Jul 26 07:05:51 PM PDT 24 |
9975984348 ps |
| T816 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.1739401830 |
|
|
Jul 26 07:02:31 PM PDT 24 |
Jul 26 07:13:26 PM PDT 24 |
13054804451 ps |
| T817 |
/workspace/coverage/default/34.sram_ctrl_mem_partial_access.1266812002 |
|
|
Jul 26 07:05:08 PM PDT 24 |
Jul 26 07:06:23 PM PDT 24 |
5583439163 ps |
| T818 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.4148412605 |
|
|
Jul 26 07:04:13 PM PDT 24 |
Jul 26 07:09:04 PM PDT 24 |
4688142759 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.1729360316 |
|
|
Jul 26 07:07:13 PM PDT 24 |
Jul 26 07:11:23 PM PDT 24 |
43224855737 ps |
| T820 |
/workspace/coverage/default/33.sram_ctrl_mem_partial_access.3955590435 |
|
|
Jul 26 07:05:02 PM PDT 24 |
Jul 26 07:06:32 PM PDT 24 |
3193403000 ps |
| T821 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.1874636086 |
|
|
Jul 26 07:04:49 PM PDT 24 |
Jul 26 07:05:00 PM PDT 24 |
272493385 ps |
| T822 |
/workspace/coverage/default/35.sram_ctrl_bijection.959926558 |
|
|
Jul 26 07:05:09 PM PDT 24 |
Jul 26 07:27:56 PM PDT 24 |
61190152281 ps |
| T823 |
/workspace/coverage/default/7.sram_ctrl_executable.3022809222 |
|
|
Jul 26 07:02:48 PM PDT 24 |
Jul 26 07:14:23 PM PDT 24 |
18081560680 ps |
| T824 |
/workspace/coverage/default/31.sram_ctrl_mem_partial_access.1864920341 |
|
|
Jul 26 07:04:47 PM PDT 24 |
Jul 26 07:07:27 PM PDT 24 |
11803361982 ps |
| T825 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.2591681458 |
|
|
Jul 26 07:02:35 PM PDT 24 |
Jul 26 07:02:39 PM PDT 24 |
349845251 ps |
| T826 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2558086415 |
|
|
Jul 26 07:02:49 PM PDT 24 |
Jul 26 07:03:04 PM PDT 24 |
1479019640 ps |
| T827 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.2668225781 |
|
|
Jul 26 07:02:14 PM PDT 24 |
Jul 26 07:02:22 PM PDT 24 |
2908582236 ps |
| T828 |
/workspace/coverage/default/44.sram_ctrl_regwen.646557232 |
|
|
Jul 26 07:07:07 PM PDT 24 |
Jul 26 07:19:59 PM PDT 24 |
15591481896 ps |
| T829 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.2099326218 |
|
|
Jul 26 07:02:16 PM PDT 24 |
Jul 26 07:02:25 PM PDT 24 |
726965308 ps |
| T830 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.2553776144 |
|
|
Jul 26 07:05:47 PM PDT 24 |
Jul 26 07:05:50 PM PDT 24 |
770730293 ps |
| T831 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.3549854595 |
|
|
Jul 26 07:03:45 PM PDT 24 |
Jul 26 07:06:08 PM PDT 24 |
5118518267 ps |
| T832 |
/workspace/coverage/default/18.sram_ctrl_stress_all.1893568683 |
|
|
Jul 26 07:03:23 PM PDT 24 |
Jul 26 07:36:49 PM PDT 24 |
38666233707 ps |
| T833 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2186092241 |
|
|
Jul 26 07:02:48 PM PDT 24 |
Jul 26 07:10:23 PM PDT 24 |
86890764788 ps |
| T834 |
/workspace/coverage/default/37.sram_ctrl_bijection.905401924 |
|
|
Jul 26 07:05:31 PM PDT 24 |
Jul 26 07:33:05 PM PDT 24 |
345360118618 ps |
| T835 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.2721299049 |
|
|
Jul 26 07:07:25 PM PDT 24 |
Jul 26 07:07:29 PM PDT 24 |
1025958626 ps |
| T836 |
/workspace/coverage/default/48.sram_ctrl_executable.1788918506 |
|
|
Jul 26 07:08:03 PM PDT 24 |
Jul 26 07:13:52 PM PDT 24 |
12985447756 ps |
| T837 |
/workspace/coverage/default/4.sram_ctrl_bijection.1780196438 |
|
|
Jul 26 07:02:45 PM PDT 24 |
Jul 26 07:40:19 PM PDT 24 |
101254695644 ps |
| T838 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3164470422 |
|
|
Jul 26 07:06:24 PM PDT 24 |
Jul 26 07:13:22 PM PDT 24 |
13313801615 ps |
| T839 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3850735830 |
|
|
Jul 26 07:03:54 PM PDT 24 |
Jul 26 07:07:33 PM PDT 24 |
15139048656 ps |
| T840 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.2398287173 |
|
|
Jul 26 07:02:36 PM PDT 24 |
Jul 26 07:09:59 PM PDT 24 |
20383640956 ps |
| T841 |
/workspace/coverage/default/10.sram_ctrl_throughput_w_partial_write.3069607508 |
|
|
Jul 26 07:02:57 PM PDT 24 |
Jul 26 07:03:04 PM PDT 24 |
1486719015 ps |
| T842 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2706870813 |
|
|
Jul 26 07:03:03 PM PDT 24 |
Jul 26 07:03:04 PM PDT 24 |
13743617 ps |
| T843 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.256106857 |
|
|
Jul 26 07:03:20 PM PDT 24 |
Jul 26 07:09:00 PM PDT 24 |
3788663006 ps |
| T844 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.4090272337 |
|
|
Jul 26 07:04:40 PM PDT 24 |
Jul 26 07:04:43 PM PDT 24 |
1886964728 ps |
| T845 |
/workspace/coverage/default/29.sram_ctrl_partial_access.1158088426 |
|
|
Jul 26 07:04:20 PM PDT 24 |
Jul 26 07:04:46 PM PDT 24 |
3962254452 ps |
| T846 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.3262259263 |
|
|
Jul 26 07:05:30 PM PDT 24 |
Jul 26 07:10:11 PM PDT 24 |
49225366391 ps |
| T847 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1427770355 |
|
|
Jul 26 07:06:49 PM PDT 24 |
Jul 26 07:07:34 PM PDT 24 |
31110703319 ps |
| T848 |
/workspace/coverage/default/1.sram_ctrl_regwen.852260785 |
|
|
Jul 26 07:02:34 PM PDT 24 |
Jul 26 07:07:05 PM PDT 24 |
1391735310 ps |
| T849 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.453815695 |
|
|
Jul 26 07:03:13 PM PDT 24 |
Jul 26 07:04:38 PM PDT 24 |
4723983490 ps |
| T850 |
/workspace/coverage/default/23.sram_ctrl_regwen.1568667802 |
|
|
Jul 26 07:03:45 PM PDT 24 |
Jul 26 07:20:38 PM PDT 24 |
23468429900 ps |
| T851 |
/workspace/coverage/default/26.sram_ctrl_partial_access.3502060371 |
|
|
Jul 26 07:03:55 PM PDT 24 |
Jul 26 07:04:14 PM PDT 24 |
3380997950 ps |
| T852 |
/workspace/coverage/default/17.sram_ctrl_bijection.2629988422 |
|
|
Jul 26 07:03:05 PM PDT 24 |
Jul 26 07:18:11 PM PDT 24 |
14042654572 ps |
| T853 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.3086760425 |
|
|
Jul 26 07:06:59 PM PDT 24 |
Jul 26 07:08:23 PM PDT 24 |
6150064764 ps |
| T854 |
/workspace/coverage/default/11.sram_ctrl_access_during_key_req.2101841349 |
|
|
Jul 26 07:03:00 PM PDT 24 |
Jul 26 07:15:09 PM PDT 24 |
9856249389 ps |
| T855 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.1200558196 |
|
|
Jul 26 07:03:05 PM PDT 24 |
Jul 26 07:03:19 PM PDT 24 |
1866546005 ps |
| T30 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1842160185 |
|
|
Jul 26 07:02:25 PM PDT 24 |
Jul 26 07:02:28 PM PDT 24 |
359012105 ps |
| T856 |
/workspace/coverage/default/49.sram_ctrl_partial_access_b2b.3281307705 |
|
|
Jul 26 07:08:07 PM PDT 24 |
Jul 26 07:16:51 PM PDT 24 |
78213568889 ps |
| T857 |
/workspace/coverage/default/21.sram_ctrl_regwen.2796263297 |
|
|
Jul 26 07:03:31 PM PDT 24 |
Jul 26 07:12:44 PM PDT 24 |
45525904227 ps |
| T858 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3779108139 |
|
|
Jul 26 07:03:11 PM PDT 24 |
Jul 26 07:03:28 PM PDT 24 |
2916230289 ps |
| T859 |
/workspace/coverage/default/11.sram_ctrl_stress_all.4238838158 |
|
|
Jul 26 07:03:17 PM PDT 24 |
Jul 26 07:39:56 PM PDT 24 |
13896047445 ps |
| T860 |
/workspace/coverage/default/27.sram_ctrl_mem_walk.3283207516 |
|
|
Jul 26 07:04:04 PM PDT 24 |
Jul 26 07:06:33 PM PDT 24 |
10951310797 ps |
| T861 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1571911128 |
|
|
Jul 26 07:07:15 PM PDT 24 |
Jul 26 07:07:18 PM PDT 24 |
352232468 ps |
| T862 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.1949731927 |
|
|
Jul 26 07:02:26 PM PDT 24 |
Jul 26 07:12:48 PM PDT 24 |
38453114548 ps |
| T863 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.2307744747 |
|
|
Jul 26 07:04:19 PM PDT 24 |
Jul 26 07:09:50 PM PDT 24 |
23323323948 ps |
| T864 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.2444498578 |
|
|
Jul 26 07:06:58 PM PDT 24 |
Jul 26 07:08:02 PM PDT 24 |
9859436954 ps |
| T865 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.2996108172 |
|
|
Jul 26 07:02:51 PM PDT 24 |
Jul 26 07:05:24 PM PDT 24 |
10449354582 ps |
| T866 |
/workspace/coverage/default/18.sram_ctrl_bijection.413919536 |
|
|
Jul 26 07:03:14 PM PDT 24 |
Jul 26 07:39:02 PM PDT 24 |
116690442752 ps |
| T867 |
/workspace/coverage/default/29.sram_ctrl_regwen.313907867 |
|
|
Jul 26 07:04:30 PM PDT 24 |
Jul 26 07:20:59 PM PDT 24 |
2758246334 ps |
| T868 |
/workspace/coverage/default/46.sram_ctrl_regwen.3703298319 |
|
|
Jul 26 07:07:25 PM PDT 24 |
Jul 26 07:33:41 PM PDT 24 |
174498951220 ps |
| T869 |
/workspace/coverage/default/4.sram_ctrl_access_during_key_req.439286736 |
|
|
Jul 26 07:02:40 PM PDT 24 |
Jul 26 07:19:41 PM PDT 24 |
12901806895 ps |
| T870 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1125190442 |
|
|
Jul 26 07:02:40 PM PDT 24 |
Jul 26 07:02:43 PM PDT 24 |
377545529 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_alert_test.2940176480 |
|
|
Jul 26 07:03:16 PM PDT 24 |
Jul 26 07:03:16 PM PDT 24 |
11560216 ps |
| T872 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.2173015227 |
|
|
Jul 26 07:03:07 PM PDT 24 |
Jul 26 07:03:34 PM PDT 24 |
727642813 ps |
| T873 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.2317996283 |
|
|
Jul 26 07:03:54 PM PDT 24 |
Jul 26 07:12:12 PM PDT 24 |
8896179904 ps |
| T874 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1906469531 |
|
|
Jul 26 07:03:46 PM PDT 24 |
Jul 26 07:09:05 PM PDT 24 |
91856536237 ps |
| T875 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.715350135 |
|
|
Jul 26 07:02:48 PM PDT 24 |
Jul 26 07:03:11 PM PDT 24 |
749809949 ps |
| T876 |
/workspace/coverage/default/27.sram_ctrl_smoke.1693597135 |
|
|
Jul 26 07:04:02 PM PDT 24 |
Jul 26 07:04:23 PM PDT 24 |
3459647821 ps |
| T877 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3023867065 |
|
|
Jul 26 07:06:06 PM PDT 24 |
Jul 26 07:11:59 PM PDT 24 |
71765978555 ps |
| T878 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.713004568 |
|
|
Jul 26 07:03:55 PM PDT 24 |
Jul 26 07:09:25 PM PDT 24 |
12511108494 ps |
| T879 |
/workspace/coverage/default/13.sram_ctrl_partial_access.3114852984 |
|
|
Jul 26 07:03:05 PM PDT 24 |
Jul 26 07:03:26 PM PDT 24 |
2765207307 ps |
| T880 |
/workspace/coverage/default/17.sram_ctrl_partial_access.379728133 |
|
|
Jul 26 07:03:07 PM PDT 24 |
Jul 26 07:03:11 PM PDT 24 |
361244126 ps |
| T881 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3652270055 |
|
|
Jul 26 07:02:18 PM PDT 24 |
Jul 26 07:02:51 PM PDT 24 |
1317538774 ps |
| T882 |
/workspace/coverage/default/35.sram_ctrl_smoke.802209276 |
|
|
Jul 26 07:05:13 PM PDT 24 |
Jul 26 07:05:57 PM PDT 24 |
1107848385 ps |
| T883 |
/workspace/coverage/default/23.sram_ctrl_smoke.2009211363 |
|
|
Jul 26 07:03:45 PM PDT 24 |
Jul 26 07:04:02 PM PDT 24 |
4315830721 ps |
| T884 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.519594829 |
|
|
Jul 26 07:04:14 PM PDT 24 |
Jul 26 07:05:07 PM PDT 24 |
3048884351 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_smoke.1094127377 |
|
|
Jul 26 07:03:03 PM PDT 24 |
Jul 26 07:03:20 PM PDT 24 |
18481186045 ps |
| T886 |
/workspace/coverage/default/26.sram_ctrl_smoke.249786701 |
|
|
Jul 26 07:04:02 PM PDT 24 |
Jul 26 07:04:07 PM PDT 24 |
721348988 ps |
| T887 |
/workspace/coverage/default/43.sram_ctrl_partial_access.948726699 |
|
|
Jul 26 07:07:04 PM PDT 24 |
Jul 26 07:08:17 PM PDT 24 |
1627735803 ps |
| T888 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2836428024 |
|
|
Jul 26 07:02:46 PM PDT 24 |
Jul 26 07:05:14 PM PDT 24 |
11438322911 ps |
| T889 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.1964207386 |
|
|
Jul 26 07:04:36 PM PDT 24 |
Jul 26 07:06:01 PM PDT 24 |
2631872549 ps |
| T890 |
/workspace/coverage/default/38.sram_ctrl_partial_access_b2b.3008235746 |
|
|
Jul 26 07:05:42 PM PDT 24 |
Jul 26 07:10:36 PM PDT 24 |
5408731748 ps |
| T891 |
/workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.4076815360 |
|
|
Jul 26 07:07:56 PM PDT 24 |
Jul 26 07:08:37 PM PDT 24 |
975997077 ps |
| T892 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.1463609247 |
|
|
Jul 26 07:05:52 PM PDT 24 |
Jul 26 07:07:01 PM PDT 24 |
12305627791 ps |
| T893 |
/workspace/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.2280854875 |
|
|
Jul 26 07:02:32 PM PDT 24 |
Jul 26 07:02:53 PM PDT 24 |
699738082 ps |
| T894 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.2320866390 |
|
|
Jul 26 07:02:14 PM PDT 24 |
Jul 26 07:30:01 PM PDT 24 |
164842361987 ps |
| T895 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.2208604259 |
|
|
Jul 26 07:03:58 PM PDT 24 |
Jul 26 07:09:27 PM PDT 24 |
74812858923 ps |
| T896 |
/workspace/coverage/default/12.sram_ctrl_stress_pipeline.4009570655 |
|
|
Jul 26 07:02:56 PM PDT 24 |
Jul 26 07:07:47 PM PDT 24 |
9428377357 ps |
| T897 |
/workspace/coverage/default/47.sram_ctrl_bijection.848807018 |
|
|
Jul 26 07:07:36 PM PDT 24 |
Jul 26 07:24:58 PM PDT 24 |
48109728189 ps |
| T898 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.701064922 |
|
|
Jul 26 07:05:17 PM PDT 24 |
Jul 26 07:06:31 PM PDT 24 |
2909030419 ps |
| T899 |
/workspace/coverage/default/19.sram_ctrl_alert_test.3755975848 |
|
|
Jul 26 07:03:18 PM PDT 24 |
Jul 26 07:03:19 PM PDT 24 |
15768972 ps |
| T900 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3343916617 |
|
|
Jul 26 07:03:30 PM PDT 24 |
Jul 26 07:04:00 PM PDT 24 |
7949639737 ps |
| T901 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1295566174 |
|
|
Jul 26 07:03:04 PM PDT 24 |
Jul 26 07:04:19 PM PDT 24 |
780208392 ps |
| T902 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.812736995 |
|
|
Jul 26 07:02:43 PM PDT 24 |
Jul 26 07:02:51 PM PDT 24 |
862418208 ps |
| T903 |
/workspace/coverage/default/16.sram_ctrl_regwen.941616468 |
|
|
Jul 26 07:03:10 PM PDT 24 |
Jul 26 07:25:46 PM PDT 24 |
37390699023 ps |
| T904 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.2477085931 |
|
|
Jul 26 07:06:37 PM PDT 24 |
Jul 26 07:07:23 PM PDT 24 |
8029956829 ps |
| T905 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.2965315162 |
|
|
Jul 26 07:07:07 PM PDT 24 |
Jul 26 07:13:17 PM PDT 24 |
5803142129 ps |
| T906 |
/workspace/coverage/default/38.sram_ctrl_smoke.693176841 |
|
|
Jul 26 07:05:43 PM PDT 24 |
Jul 26 07:05:53 PM PDT 24 |
756258756 ps |
| T907 |
/workspace/coverage/default/7.sram_ctrl_partial_access_b2b.1217625455 |
|
|
Jul 26 07:02:44 PM PDT 24 |
Jul 26 07:07:51 PM PDT 24 |
129443948656 ps |
| T908 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1811785294 |
|
|
Jul 26 07:03:10 PM PDT 24 |
Jul 26 07:08:34 PM PDT 24 |
14009187815 ps |
| T909 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.3216106101 |
|
|
Jul 26 07:05:18 PM PDT 24 |
Jul 26 07:05:29 PM PDT 24 |
3812064575 ps |
| T910 |
/workspace/coverage/default/29.sram_ctrl_alert_test.4133209016 |
|
|
Jul 26 07:04:30 PM PDT 24 |
Jul 26 07:04:31 PM PDT 24 |
34379763 ps |
| T911 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1943387625 |
|
|
Jul 26 07:02:57 PM PDT 24 |
Jul 26 07:03:01 PM PDT 24 |
386950905 ps |
| T912 |
/workspace/coverage/default/31.sram_ctrl_stress_all.3806059042 |
|
|
Jul 26 07:04:46 PM PDT 24 |
Jul 26 08:07:30 PM PDT 24 |
1542179796288 ps |
| T913 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2333740869 |
|
|
Jul 26 07:04:30 PM PDT 24 |
Jul 26 07:22:15 PM PDT 24 |
15280215776 ps |
| T914 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3370448923 |
|
|
Jul 26 07:05:00 PM PDT 24 |
Jul 26 07:14:04 PM PDT 24 |
23064720484 ps |
| T915 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.569004938 |
|
|
Jul 26 07:05:53 PM PDT 24 |
Jul 26 07:12:39 PM PDT 24 |
71374744477 ps |
| T916 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.883088184 |
|
|
Jul 26 07:02:32 PM PDT 24 |
Jul 26 07:05:52 PM PDT 24 |
3068313537 ps |
| T917 |
/workspace/coverage/default/35.sram_ctrl_regwen.2537934391 |
|
|
Jul 26 07:05:18 PM PDT 24 |
Jul 26 07:15:52 PM PDT 24 |
4927059666 ps |
| T918 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.1021920209 |
|
|
Jul 26 07:03:01 PM PDT 24 |
Jul 26 07:07:40 PM PDT 24 |
21668338988 ps |
| T919 |
/workspace/coverage/default/6.sram_ctrl_bijection.552157374 |
|
|
Jul 26 07:02:48 PM PDT 24 |
Jul 26 07:31:18 PM PDT 24 |
414361764666 ps |
| T920 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.3229267 |
|
|
Jul 26 07:02:46 PM PDT 24 |
Jul 26 07:06:32 PM PDT 24 |
6127528525 ps |
| T921 |
/workspace/coverage/default/34.sram_ctrl_partial_access.1880484077 |
|
|
Jul 26 07:05:01 PM PDT 24 |
Jul 26 07:05:15 PM PDT 24 |
5261624088 ps |
| T922 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1471797766 |
|
|
Jul 26 07:04:19 PM PDT 24 |
Jul 26 07:04:23 PM PDT 24 |
351452891 ps |
| T923 |
/workspace/coverage/default/5.sram_ctrl_regwen.1604135414 |
|
|
Jul 26 07:02:48 PM PDT 24 |
Jul 26 07:13:42 PM PDT 24 |
20601775915 ps |
| T924 |
/workspace/coverage/default/35.sram_ctrl_stress_pipeline.591723745 |
|
|
Jul 26 07:05:17 PM PDT 24 |
Jul 26 07:10:27 PM PDT 24 |
3554738502 ps |
| T925 |
/workspace/coverage/default/12.sram_ctrl_partial_access.2857156600 |
|
|
Jul 26 07:02:58 PM PDT 24 |
Jul 26 07:03:25 PM PDT 24 |
19025300487 ps |
| T926 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.991426620 |
|
|
Jul 26 07:03:55 PM PDT 24 |
Jul 26 07:05:02 PM PDT 24 |
6025525313 ps |
| T927 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3180573839 |
|
|
Jul 26 07:02:40 PM PDT 24 |
Jul 26 07:04:03 PM PDT 24 |
7940630102 ps |
| T928 |
/workspace/coverage/default/40.sram_ctrl_smoke.107140779 |
|
|
Jul 26 07:06:05 PM PDT 24 |
Jul 26 07:08:31 PM PDT 24 |
18941284918 ps |
| T929 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.1512098891 |
|
|
Jul 26 07:03:55 PM PDT 24 |
Jul 26 07:09:37 PM PDT 24 |
82677205892 ps |
| T930 |
/workspace/coverage/default/40.sram_ctrl_bijection.1434627797 |
|
|
Jul 26 07:06:07 PM PDT 24 |
Jul 26 07:38:54 PM PDT 24 |
106213239535 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.1784921633 |
|
|
Jul 26 07:03:04 PM PDT 24 |
Jul 26 07:06:04 PM PDT 24 |
6467528437 ps |
| T932 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.839235195 |
|
|
Jul 26 07:05:16 PM PDT 24 |
Jul 26 07:19:52 PM PDT 24 |
33291034507 ps |
| T933 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.2876392398 |
|
|
Jul 26 07:08:08 PM PDT 24 |
Jul 26 07:08:46 PM PDT 24 |
4993249814 ps |
| T934 |
/workspace/coverage/default/46.sram_ctrl_stress_all.1514758845 |
|
|
Jul 26 07:07:36 PM PDT 24 |
Jul 26 08:56:12 PM PDT 24 |
148284281795 ps |
| T935 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.346137680 |
|
|
Jul 26 07:03:56 PM PDT 24 |
Jul 26 07:04:06 PM PDT 24 |
2421941263 ps |
| T936 |
/workspace/coverage/default/27.sram_ctrl_multiple_keys.105439225 |
|
|
Jul 26 07:04:12 PM PDT 24 |
Jul 26 07:21:10 PM PDT 24 |
58305875005 ps |
| T937 |
/workspace/coverage/default/18.sram_ctrl_smoke.557138104 |
|
|
Jul 26 07:03:21 PM PDT 24 |
Jul 26 07:03:31 PM PDT 24 |
3152208913 ps |
| T938 |
/workspace/coverage/default/40.sram_ctrl_stress_all.1046502617 |
|
|
Jul 26 07:06:15 PM PDT 24 |
Jul 26 09:04:00 PM PDT 24 |
930250171929 ps |
| T939 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.2342299744 |
|
|
Jul 26 07:02:59 PM PDT 24 |
Jul 26 07:05:47 PM PDT 24 |
10339073297 ps |
| T940 |
/workspace/coverage/default/31.sram_ctrl_partial_access.2054908097 |
|
|
Jul 26 07:04:37 PM PDT 24 |
Jul 26 07:04:42 PM PDT 24 |
4300122011 ps |
| T941 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3483663498 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:09 PM PDT 24 |
421649013 ps |
| T942 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.831915751 |
|
|
Jul 26 06:57:23 PM PDT 24 |
Jul 26 06:57:27 PM PDT 24 |
208801894 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1422502640 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:59 PM PDT 24 |
199551337 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.11353681 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:44 PM PDT 24 |
342526577 ps |
| T944 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2015437165 |
|
|
Jul 26 06:57:12 PM PDT 24 |
Jul 26 06:57:16 PM PDT 24 |
369604136 ps |
| T945 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.705049773 |
|
|
Jul 26 06:56:40 PM PDT 24 |
Jul 26 06:56:45 PM PDT 24 |
4411915238 ps |
| T68 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3935634507 |
|
|
Jul 26 06:57:19 PM PDT 24 |
Jul 26 06:57:20 PM PDT 24 |
48238955 ps |
| T69 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.61037220 |
|
|
Jul 26 06:56:24 PM PDT 24 |
Jul 26 06:56:26 PM PDT 24 |
193324509 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.3788141976 |
|
|
Jul 26 06:56:32 PM PDT 24 |
Jul 26 06:57:23 PM PDT 24 |
7156686714 ps |
| T101 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3730358159 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:05 PM PDT 24 |
25381354 ps |
| T946 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.1828679930 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:18 PM PDT 24 |
761673398 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.408824716 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:18 PM PDT 24 |
580733691 ps |
| T79 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3248235498 |
|
|
Jul 26 06:57:19 PM PDT 24 |
Jul 26 06:58:13 PM PDT 24 |
14425617801 ps |
| T66 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.121322094 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
758647891 ps |
| T67 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1350208867 |
|
|
Jul 26 06:56:24 PM PDT 24 |
Jul 26 06:56:27 PM PDT 24 |
409762073 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.2533451545 |
|
|
Jul 26 06:56:33 PM PDT 24 |
Jul 26 06:56:34 PM PDT 24 |
17521897 ps |
| T80 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3505064443 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:33 PM PDT 24 |
16763298976 ps |
| T102 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.84256230 |
|
|
Jul 26 06:56:51 PM PDT 24 |
Jul 26 06:56:52 PM PDT 24 |
102432518 ps |
| T115 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3388925479 |
|
|
Jul 26 06:56:16 PM PDT 24 |
Jul 26 06:56:18 PM PDT 24 |
1273643160 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.335945580 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:15 PM PDT 24 |
52920576 ps |
| T130 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2961805991 |
|
|
Jul 26 06:56:50 PM PDT 24 |
Jul 26 06:56:52 PM PDT 24 |
369741880 ps |
| T949 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2835197296 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:14 PM PDT 24 |
20403397 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.4253201026 |
|
|
Jul 26 06:56:58 PM PDT 24 |
Jul 26 06:57:01 PM PDT 24 |
328918153 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3582582139 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:09 PM PDT 24 |
1006403764 ps |
| T952 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1414231202 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:17 PM PDT 24 |
140907635 ps |
| T104 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.3775388556 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
44117918 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.657382367 |
|
|
Jul 26 06:57:20 PM PDT 24 |
Jul 26 06:57:24 PM PDT 24 |
359005490 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1285134296 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
25734475 ps |
| T105 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2750534326 |
|
|
Jul 26 06:56:51 PM PDT 24 |
Jul 26 06:56:52 PM PDT 24 |
12380441 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.2320684253 |
|
|
Jul 26 06:56:22 PM PDT 24 |
Jul 26 06:56:23 PM PDT 24 |
14992886 ps |
| T106 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3909628918 |
|
|
Jul 26 06:56:29 PM PDT 24 |
Jul 26 06:56:30 PM PDT 24 |
16351233 ps |
| T126 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1252558112 |
|
|
Jul 26 06:57:07 PM PDT 24 |
Jul 26 06:57:10 PM PDT 24 |
327148421 ps |
| T82 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2323294813 |
|
|
Jul 26 06:56:56 PM PDT 24 |
Jul 26 06:57:26 PM PDT 24 |
15383441108 ps |
| T83 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3108338823 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:58 PM PDT 24 |
65762127 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2744936876 |
|
|
Jul 26 06:56:17 PM PDT 24 |
Jul 26 06:56:20 PM PDT 24 |
174267175 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1910885597 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:58 PM PDT 24 |
276846870 ps |
| T956 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.2007337701 |
|
|
Jul 26 06:56:16 PM PDT 24 |
Jul 26 06:56:16 PM PDT 24 |
45022978 ps |
| T957 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3669445143 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:15 PM PDT 24 |
61743020 ps |
| T84 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.1545630022 |
|
|
Jul 26 06:56:30 PM PDT 24 |
Jul 26 06:56:31 PM PDT 24 |
16283061 ps |
| T958 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1341617739 |
|
|
Jul 26 06:56:34 PM PDT 24 |
Jul 26 06:56:36 PM PDT 24 |
120672962 ps |
| T132 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2909650231 |
|
|
Jul 26 06:56:24 PM PDT 24 |
Jul 26 06:56:27 PM PDT 24 |
540330479 ps |
| T959 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2463509728 |
|
|
Jul 26 06:56:33 PM PDT 24 |
Jul 26 06:56:35 PM PDT 24 |
235555985 ps |
| T85 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.61415219 |
|
|
Jul 26 06:57:12 PM PDT 24 |
Jul 26 06:57:13 PM PDT 24 |
15997789 ps |
| T960 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2558105721 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:14 PM PDT 24 |
38371381 ps |
| T86 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2011166201 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:58:01 PM PDT 24 |
7742282208 ps |
| T961 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2671791430 |
|
|
Jul 26 06:56:51 PM PDT 24 |
Jul 26 06:56:52 PM PDT 24 |
37611940 ps |
| T962 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.3801335814 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
22839521 ps |
| T127 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1771671192 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
88661513 ps |
| T963 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2754690229 |
|
|
Jul 26 06:57:15 PM PDT 24 |
Jul 26 06:57:19 PM PDT 24 |
387351114 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1226186582 |
|
|
Jul 26 06:56:17 PM PDT 24 |
Jul 26 06:56:48 PM PDT 24 |
13642736905 ps |
| T88 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.67938987 |
|
|
Jul 26 06:56:50 PM PDT 24 |
Jul 26 06:57:39 PM PDT 24 |
28344490890 ps |
| T137 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.69130151 |
|
|
Jul 26 06:57:22 PM PDT 24 |
Jul 26 06:57:25 PM PDT 24 |
1085890061 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.4054732363 |
|
|
Jul 26 06:56:51 PM PDT 24 |
Jul 26 06:56:56 PM PDT 24 |
341757079 ps |
| T89 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2579685869 |
|
|
Jul 26 06:56:32 PM PDT 24 |
Jul 26 06:56:33 PM PDT 24 |
14970284 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.402748283 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:45 PM PDT 24 |
366000630 ps |
| T966 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2333742578 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:09 PM PDT 24 |
443699514 ps |
| T967 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2763430973 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:57:02 PM PDT 24 |
3833116185 ps |
| T968 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.2091252430 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:58 PM PDT 24 |
14651214 ps |
| T969 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3273783841 |
|
|
Jul 26 06:56:49 PM PDT 24 |
Jul 26 06:56:53 PM PDT 24 |
356858029 ps |
| T129 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.534233133 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:43 PM PDT 24 |
622059682 ps |
| T133 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3961850066 |
|
|
Jul 26 06:56:32 PM PDT 24 |
Jul 26 06:56:34 PM PDT 24 |
154972844 ps |
| T970 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.853311048 |
|
|
Jul 26 06:56:50 PM PDT 24 |
Jul 26 06:56:53 PM PDT 24 |
2256139063 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1676583842 |
|
|
Jul 26 06:56:31 PM PDT 24 |
Jul 26 06:56:33 PM PDT 24 |
763350129 ps |
| T972 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2290190324 |
|
|
Jul 26 06:56:33 PM PDT 24 |
Jul 26 06:56:34 PM PDT 24 |
15957249 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.569647892 |
|
|
Jul 26 06:57:20 PM PDT 24 |
Jul 26 06:57:21 PM PDT 24 |
12778090 ps |
| T90 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2127264038 |
|
|
Jul 26 06:56:17 PM PDT 24 |
Jul 26 06:56:45 PM PDT 24 |
3836523804 ps |
| T974 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1439887388 |
|
|
Jul 26 06:57:06 PM PDT 24 |
Jul 26 06:57:10 PM PDT 24 |
483759619 ps |
| T97 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1255538912 |
|
|
Jul 26 06:57:12 PM PDT 24 |
Jul 26 06:57:42 PM PDT 24 |
52602649821 ps |
| T975 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.138283851 |
|
|
Jul 26 06:56:17 PM PDT 24 |
Jul 26 06:56:18 PM PDT 24 |
146926531 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1729412836 |
|
|
Jul 26 06:56:56 PM PDT 24 |
Jul 26 06:56:59 PM PDT 24 |
317006220 ps |
| T977 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.669893686 |
|
|
Jul 26 06:57:15 PM PDT 24 |
Jul 26 06:57:19 PM PDT 24 |
266453548 ps |
| T978 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1660446526 |
|
|
Jul 26 06:57:04 PM PDT 24 |
Jul 26 06:57:08 PM PDT 24 |
1293037122 ps |
| T979 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.1928166032 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
31551605 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.2340223758 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:42 PM PDT 24 |
29727548 ps |
| T95 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2278000276 |
|
|
Jul 26 06:57:06 PM PDT 24 |
Jul 26 06:57:33 PM PDT 24 |
15383273574 ps |
| T96 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.524452906 |
|
|
Jul 26 06:56:49 PM PDT 24 |
Jul 26 06:56:50 PM PDT 24 |
21974751 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2807024183 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:59 PM PDT 24 |
213022024 ps |
| T134 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3937847497 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:15 PM PDT 24 |
632781809 ps |
| T982 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.544465218 |
|
|
Jul 26 06:57:13 PM PDT 24 |
Jul 26 06:57:14 PM PDT 24 |
38746183 ps |
| T983 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2022583389 |
|
|
Jul 26 06:57:22 PM PDT 24 |
Jul 26 06:57:26 PM PDT 24 |
356101538 ps |
| T984 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.2766042450 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:15 PM PDT 24 |
44106450 ps |
| T985 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.538772192 |
|
|
Jul 26 06:57:06 PM PDT 24 |
Jul 26 06:58:04 PM PDT 24 |
47015226791 ps |
| T986 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.3627678502 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:57:06 PM PDT 24 |
37366424 ps |
| T135 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.931152450 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:17 PM PDT 24 |
500349660 ps |
| T987 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2949031982 |
|
|
Jul 26 06:57:15 PM PDT 24 |
Jul 26 06:57:19 PM PDT 24 |
1774723264 ps |
| T988 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3705162572 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:42 PM PDT 24 |
15576426 ps |
| T989 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3943788613 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:56:42 PM PDT 24 |
12534044 ps |
| T990 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2379758793 |
|
|
Jul 26 06:56:39 PM PDT 24 |
Jul 26 06:56:44 PM PDT 24 |
306272101 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2494151984 |
|
|
Jul 26 06:56:25 PM PDT 24 |
Jul 26 06:56:26 PM PDT 24 |
51141517 ps |
| T992 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.436273855 |
|
|
Jul 26 06:57:06 PM PDT 24 |
Jul 26 06:57:08 PM PDT 24 |
52704304 ps |
| T993 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.693294236 |
|
|
Jul 26 06:56:23 PM PDT 24 |
Jul 26 06:56:28 PM PDT 24 |
2481908776 ps |
| T994 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.4001141310 |
|
|
Jul 26 06:57:14 PM PDT 24 |
Jul 26 06:57:43 PM PDT 24 |
3775050141 ps |
| T995 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1086234185 |
|
|
Jul 26 06:56:48 PM PDT 24 |
Jul 26 06:56:53 PM PDT 24 |
174909315 ps |
| T996 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.912227748 |
|
|
Jul 26 06:56:52 PM PDT 24 |
Jul 26 06:56:55 PM PDT 24 |
2049187330 ps |
| T98 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2444018940 |
|
|
Jul 26 06:56:57 PM PDT 24 |
Jul 26 06:56:57 PM PDT 24 |
23306974 ps |
| T997 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.2895993670 |
|
|
Jul 26 06:56:24 PM PDT 24 |
Jul 26 06:56:25 PM PDT 24 |
38501427 ps |
| T99 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1579649185 |
|
|
Jul 26 06:56:41 PM PDT 24 |
Jul 26 06:57:08 PM PDT 24 |
3883437402 ps |
| T100 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3809811022 |
|
|
Jul 26 06:56:17 PM PDT 24 |
Jul 26 06:56:18 PM PDT 24 |
33438337 ps |
| T998 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1337139335 |
|
|
Jul 26 06:56:22 PM PDT 24 |
Jul 26 06:56:25 PM PDT 24 |
251031818 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.2659732171 |
|
|
Jul 26 06:57:05 PM PDT 24 |
Jul 26 06:58:05 PM PDT 24 |
78262547680 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.866133443 |
|
|
Jul 26 06:56:23 PM PDT 24 |
Jul 26 06:56:24 PM PDT 24 |
16501769 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1202801192 |
|
|
Jul 26 06:56:50 PM PDT 24 |
Jul 26 06:57:19 PM PDT 24 |
3714563601 ps |
| T1002 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2913452027 |
|
|
Jul 26 06:56:25 PM PDT 24 |
Jul 26 06:57:18 PM PDT 24 |
50334066727 ps |