Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16639677	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155615546

1

T1

720896

T2

9108

T3

7006

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84796696	1			T1	360448		T2	4914		T3	4284
values[0x0]	42074052	1			T1	180830		T2	2447		T3	1964
values[0x1]	45384475	1			T1	179618		T2	2663		T3	2269

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8450645	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

163804578

1

T1

720896

T2

9578

T3

7747

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	619273	1			T1	2664		T2	42		T3	31
valid_sources[0x01]	686200	1			T1	2819		T2	32		T3	44
valid_sources[0x02]	617685	1			T1	2814		T2	42		T3	35
valid_sources[0x03]	2077555	1			T1	2547		T2	39		T3	27
valid_sources[0x04]	653893	1			T1	2840		T2	36		T3	39
valid_sources[0x05]	591430	1			T1	2671		T2	43		T3	32
valid_sources[0x06]	598236	1			T1	2606		T2	41		T3	31
valid_sources[0x07]	578775	1			T1	2833		T2	41		T3	31
valid_sources[0x08]	564776	1			T1	2959		T2	42		T3	25
valid_sources[0x09]	565908	1			T1	2896		T2	39		T3	38
valid_sources[0x0a]	569707	1			T1	2619		T2	45		T3	41
valid_sources[0x0b]	654625	1			T1	2988		T2	40		T3	48
valid_sources[0x0c]	603473	1			T1	2808		T2	45		T3	31
valid_sources[0x0d]	581832	1			T1	2863		T2	36		T3	32
valid_sources[0x0e]	563282	1			T1	2902		T2	40		T3	34
valid_sources[0x0f]	620656	1			T1	2914		T2	41		T3	34
valid_sources[0x10]	636890	1			T1	2833		T2	21		T3	30
valid_sources[0x11]	646293	1			T1	2510		T2	37		T3	33
valid_sources[0x12]	566872	1			T1	3000		T2	48		T3	47
valid_sources[0x13]	578666	1			T1	3056		T2	43		T3	33
valid_sources[0x14]	574297	1			T1	2758		T2	45		T3	29
valid_sources[0x15]	1977222	1			T1	2833		T2	43		T3	25
valid_sources[0x16]	582652	1			T1	2472		T2	49		T3	28
valid_sources[0x17]	571051	1			T1	2666		T2	37		T3	22
valid_sources[0x18]	603582	1			T1	2870		T2	35		T3	40
valid_sources[0x19]	579018	1			T1	2692		T2	40		T3	29
valid_sources[0x1a]	629834	1			T1	2777		T2	48		T3	25
valid_sources[0x1b]	593041	1			T1	2732		T2	48		T3	32
valid_sources[0x1c]	582128	1			T1	2868		T2	44		T3	32
valid_sources[0x1d]	585585	1			T1	2700		T2	49		T3	26
valid_sources[0x1e]	589138	1			T1	2940		T2	31		T3	33
valid_sources[0x1f]	558537	1			T1	2785		T2	38		T3	32
valid_sources[0x20]	589686	1			T1	2984		T2	33		T3	29
valid_sources[0x21]	2232366	1			T1	2742		T2	38		T3	40
valid_sources[0x22]	580371	1			T1	2894		T2	39		T3	31
valid_sources[0x23]	633544	1			T1	2575		T2	36		T3	29
valid_sources[0x24]	797590	1			T1	2847		T2	33		T3	27
valid_sources[0x25]	610899	1			T1	2876		T2	33		T3	42
valid_sources[0x26]	583481	1			T1	2637		T2	42		T3	34
valid_sources[0x27]	579326	1			T1	2757		T2	35		T3	34
valid_sources[0x28]	650483	1			T1	2648		T2	44		T3	26
valid_sources[0x29]	563430	1			T1	2777		T2	36		T3	36
valid_sources[0x2a]	575315	1			T1	2936		T2	31		T3	38
valid_sources[0x2b]	604923	1			T1	2798		T2	38		T3	29
valid_sources[0x2c]	572643	1			T1	3033		T2	55		T3	35
valid_sources[0x2d]	591315	1			T1	2924		T2	45		T3	39
valid_sources[0x2e]	587029	1			T1	3119		T2	40		T3	31
valid_sources[0x2f]	552478	1			T1	2880		T2	34		T3	33
valid_sources[0x30]	633584	1			T1	2979		T2	34		T3	34
valid_sources[0x31]	1569226	1			T1	2804		T2	41		T3	42
valid_sources[0x32]	552867	1			T1	2556		T2	36		T3	37
valid_sources[0x33]	561442	1			T1	2876		T2	41		T3	33
valid_sources[0x34]	555477	1			T1	3016		T2	38		T3	31
valid_sources[0x35]	549956	1			T1	2963		T2	42		T3	25
valid_sources[0x36]	591416	1			T1	2503		T2	38		T3	48
valid_sources[0x37]	553526	1			T1	3012		T2	39		T3	45
valid_sources[0x38]	568081	1			T1	3020		T2	36		T3	42
valid_sources[0x39]	627105	1			T1	2807		T2	37		T3	37
valid_sources[0x3a]	611252	1			T1	2882		T2	35		T3	47
valid_sources[0x3b]	569281	1			T1	2811		T2	32		T3	28
valid_sources[0x3c]	606044	1			T1	2824		T2	41		T3	35
valid_sources[0x3d]	572622	1			T1	2762		T2	44		T3	27
valid_sources[0x3e]	592757	1			T1	2639		T2	51		T3	31
valid_sources[0x3f]	560825	1			T1	2728		T2	42		T3	29
valid_sources[0x40]	589161	1			T1	2749		T2	44		T3	51
valid_sources[0x41]	610452	1			T1	2716		T2	49		T3	34
valid_sources[0x42]	591917	1			T1	2789		T2	40		T3	27
valid_sources[0x43]	554188	1			T1	2595		T2	39		T3	39
valid_sources[0x44]	627201	1			T1	2710		T2	48		T3	18
valid_sources[0x45]	563319	1			T1	2946		T2	37		T3	29
valid_sources[0x46]	612059	1			T1	2974		T2	36		T3	47
valid_sources[0x47]	642896	1			T1	2815		T2	40		T3	26
valid_sources[0x48]	564247	1			T1	2612		T2	35		T3	29
valid_sources[0x49]	598338	1			T1	2910		T2	39		T3	32
valid_sources[0x4a]	664384	1			T1	2753		T2	41		T3	38
valid_sources[0x4b]	566943	1			T1	2610		T2	42		T3	25
valid_sources[0x4c]	581652	1			T1	2660		T2	30		T3	37
valid_sources[0x4d]	585422	1			T1	2744		T2	37		T3	39
valid_sources[0x4e]	708900	1			T1	2593		T2	37		T3	44
valid_sources[0x4f]	565475	1			T1	2874		T2	48		T3	26
valid_sources[0x50]	584689	1			T1	3000		T2	32		T3	39
valid_sources[0x51]	555545	1			T1	2855		T2	41		T3	26
valid_sources[0x52]	557725	1			T1	2876		T2	50		T3	52
valid_sources[0x53]	588654	1			T1	3018		T2	41		T3	30
valid_sources[0x54]	565853	1			T1	2717		T2	33		T3	33
valid_sources[0x55]	656194	1			T1	2723		T2	49		T3	32
valid_sources[0x56]	556093	1			T1	2733		T2	41		T3	35
valid_sources[0x57]	584641	1			T1	2641		T2	35		T3	26
valid_sources[0x58]	562153	1			T1	2923		T2	37		T3	30
valid_sources[0x59]	595452	1			T1	3016		T2	48		T3	26
valid_sources[0x5a]	556056	1			T1	2499		T2	33		T3	31
valid_sources[0x5b]	576413	1			T1	3067		T2	46		T3	41
valid_sources[0x5c]	589731	1			T1	3038		T2	36		T3	50
valid_sources[0x5d]	587583	1			T1	3000		T2	37		T3	25
valid_sources[0x5e]	597375	1			T1	2467		T2	46		T3	31
valid_sources[0x5f]	600718	1			T1	3016		T2	39		T3	46
valid_sources[0x60]	569760	1			T1	2991		T2	51		T3	31
valid_sources[0x61]	598451	1			T1	2765		T2	39		T3	21
valid_sources[0x62]	557080	1			T1	2899		T2	32		T3	27
valid_sources[0x63]	558540	1			T1	2996		T2	37		T3	33
valid_sources[0x64]	632083	1			T1	2727		T2	44		T3	28
valid_sources[0x65]	552828	1			T1	3006		T2	44		T3	33
valid_sources[0x66]	620663	1			T1	2546		T2	36		T3	24
valid_sources[0x67]	590387	1			T1	3072		T2	41		T3	32
valid_sources[0x68]	739567	1			T1	2908		T2	36		T3	46
valid_sources[0x69]	591463	1			T1	2727		T2	41		T3	37
valid_sources[0x6a]	557912	1			T1	2966		T2	37		T3	42
valid_sources[0x6b]	785197	1			T1	2909		T2	51		T3	29
valid_sources[0x6c]	1779061	1			T1	2892		T2	42		T3	27
valid_sources[0x6d]	1166763	1			T1	2896		T2	35		T3	34
valid_sources[0x6e]	590380	1			T1	2750		T2	35		T3	27
valid_sources[0x6f]	571581	1			T1	2802		T2	28		T3	34
valid_sources[0x70]	599427	1			T1	2710		T2	46		T3	35
valid_sources[0x71]	1841865	1			T1	2693		T2	43		T3	42
valid_sources[0x72]	583659	1			T1	2572		T2	41		T3	41
valid_sources[0x73]	656380	1			T1	2988		T2	45		T3	37
valid_sources[0x74]	609977	1			T1	2776		T2	40		T3	29
valid_sources[0x75]	579544	1			T1	2621		T2	33		T3	29
valid_sources[0x76]	579906	1			T1	2866		T2	47		T3	53
valid_sources[0x77]	558899	1			T1	2709		T2	35		T3	30
valid_sources[0x78]	568109	1			T1	2784		T2	34		T3	30
valid_sources[0x79]	614780	1			T1	2841		T2	41		T3	33
valid_sources[0x7a]	577776	1			T1	2923		T2	34		T3	45
valid_sources[0x7b]	609222	1			T1	2989		T2	40		T3	30
valid_sources[0x7c]	591509	1			T1	3028		T2	47		T3	32
valid_sources[0x7d]	554362	1			T1	2968		T2	40		T3	38
valid_sources[0x7e]	563221	1			T1	2701		T2	40		T3	26
valid_sources[0x7f]	567405	1			T1	2808		T2	55		T3	34
valid_sources[0x80]	567382	1			T1	2883		T2	31		T3	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

76436731

1

T1

360448

T2

4452

T3

3517

values[0x0]

all_enables

biggest_size

39591036

1

T1

180830

T2

2326

T3

1733

values[0x1]

all_enables

biggest_size

39587779

1

T1

179618

T2

2330

T3

1756

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	46915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156143

1

T1

3

T3

1

T4

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55978	1			T22	16		T27	899		T30	17
values[0x0]	71138	1			T1	5		T3	2		T4	10
values[0x1]	75942	1			T1	6		T2	2		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	36593	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

166465

1

T1

4

T3

1

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	844	1			T27	178		T6	1		T69	15
valid_sources[0x01]	744	1			T30	2		T6	2		T143	1
valid_sources[0x02]	548	1			T45	1		T27	2		T23	1
valid_sources[0x03]	621	1			T22	1		T7	1		T70	3
valid_sources[0x04]	940	1			T27	12		T30	1		T70	1
valid_sources[0x05]	908	1			T27	1		T7	1		T143	1
valid_sources[0x06]	890	1			T27	7		T143	1		T70	2
valid_sources[0x07]	648	1			T22	1		T27	7		T143	1
valid_sources[0x08]	658	1			T27	16		T24	1		T6	1
valid_sources[0x09]	586	1			T27	36		T30	1		T70	1
valid_sources[0x0a]	757	1			T70	1		T28	13		T29	15
valid_sources[0x0b]	765	1			T10	1		T28	10		T29	5
valid_sources[0x0c]	1132	1			T21	14		T144	1		T28	18
valid_sources[0x0d]	750	1			T27	3		T28	3		T29	11
valid_sources[0x0e]	852	1			T12	10		T49	1		T30	1
valid_sources[0x0f]	1042	1			T27	1		T6	1		T70	9
valid_sources[0x10]	759	1			T69	11		T28	11		T29	5
valid_sources[0x11]	668	1			T27	1		T80	1		T81	1
valid_sources[0x12]	791	1			T30	1		T28	5		T29	6
valid_sources[0x13]	889	1			T22	2		T49	2		T23	4
valid_sources[0x14]	780	1			T1	3		T81	1		T143	1
valid_sources[0x15]	708	1			T22	1		T82	1		T28	8
valid_sources[0x16]	909	1			T27	74		T70	1		T28	11
valid_sources[0x17]	659	1			T49	1		T23	5		T28	9
valid_sources[0x18]	632	1			T27	2		T82	6		T28	7
valid_sources[0x19]	901	1			T46	1		T27	1		T30	1
valid_sources[0x1a]	1216	1			T12	4		T50	107		T70	1
valid_sources[0x1b]	756	1			T22	1		T23	5		T28	6
valid_sources[0x1c]	615	1			T22	1		T27	2		T28	6
valid_sources[0x1d]	765	1			T111	1		T28	6		T29	5
valid_sources[0x1e]	1221	1			T22	2		T27	74		T145	1
valid_sources[0x1f]	766	1			T28	10		T29	13		T26	1
valid_sources[0x20]	830	1			T70	3		T28	7		T29	7
valid_sources[0x21]	1004	1			T7	1		T69	5		T70	2
valid_sources[0x22]	803	1			T30	1		T70	1		T28	5
valid_sources[0x23]	890	1			T22	1		T27	1		T30	1
valid_sources[0x24]	687	1			T22	2		T27	109		T70	3
valid_sources[0x25]	1034	1			T27	6		T23	3		T81	1
valid_sources[0x26]	598	1			T28	15		T29	13		T137	2
valid_sources[0x27]	1268	1			T27	112		T28	9		T29	8
valid_sources[0x28]	809	1			T22	1		T27	151		T28	5
valid_sources[0x29]	887	1			T22	2		T27	62		T70	4
valid_sources[0x2a]	817	1			T27	1		T28	10		T29	8
valid_sources[0x2b]	973	1			T27	2		T24	4		T111	1
valid_sources[0x2c]	699	1			T70	1		T28	4		T29	2
valid_sources[0x2d]	651	1			T10	1		T28	11		T29	9
valid_sources[0x2e]	781	1			T27	3		T30	1		T143	1
valid_sources[0x2f]	856	1			T22	1		T27	1		T23	4
valid_sources[0x30]	562	1			T27	1		T30	1		T24	1
valid_sources[0x31]	799	1			T22	1		T23	1		T70	3
valid_sources[0x32]	856	1			T27	1		T6	1		T82	1
valid_sources[0x33]	538	1			T22	1		T30	1		T81	1
valid_sources[0x34]	783	1			T27	3		T70	1		T28	10
valid_sources[0x35]	709	1			T22	1		T27	1		T23	6
valid_sources[0x36]	1138	1			T22	1		T28	14		T29	7
valid_sources[0x37]	739	1			T12	2		T22	3		T27	1
valid_sources[0x38]	717	1			T12	2		T22	1		T27	20
valid_sources[0x39]	638	1			T27	1		T30	2		T70	2
valid_sources[0x3a]	551	1			T27	8		T28	6		T29	16
valid_sources[0x3b]	913	1			T27	71		T6	2		T8	1
valid_sources[0x3c]	624	1			T49	1		T24	2		T96	3
valid_sources[0x3d]	776	1			T12	3		T49	2		T30	4
valid_sources[0x3e]	786	1			T1	2		T22	1		T7	1
valid_sources[0x3f]	763	1			T27	2		T23	3		T7	1
valid_sources[0x40]	873	1			T27	1		T6	1		T70	2
valid_sources[0x41]	919	1			T27	1		T7	1		T28	7
valid_sources[0x42]	1014	1			T22	1		T27	10		T30	1
valid_sources[0x43]	1225	1			T30	1		T146	1		T28	11
valid_sources[0x44]	978	1			T22	1		T71	7		T23	12
valid_sources[0x45]	905	1			T14	8		T27	1		T24	2
valid_sources[0x46]	892	1			T27	1		T30	1		T70	1
valid_sources[0x47]	920	1			T27	175		T8	2		T70	2
valid_sources[0x48]	885	1			T27	1		T70	1		T28	11
valid_sources[0x49]	693	1			T27	1		T30	1		T7	1
valid_sources[0x4a]	768	1			T30	1		T23	4		T7	1
valid_sources[0x4b]	756	1			T27	1		T30	1		T73	20
valid_sources[0x4c]	740	1			T22	1		T111	1		T28	13
valid_sources[0x4d]	715	1			T22	1		T30	1		T8	1
valid_sources[0x4e]	1061	1			T30	1		T28	10		T29	5
valid_sources[0x4f]	937	1			T70	1		T25	228		T28	5
valid_sources[0x50]	743	1			T22	1		T28	6		T29	7
valid_sources[0x51]	871	1			T21	5		T27	1		T6	1
valid_sources[0x52]	667	1			T49	3		T70	1		T28	13
valid_sources[0x53]	722	1			T27	1		T24	1		T8	1
valid_sources[0x54]	638	1			T27	4		T24	2		T28	4
valid_sources[0x55]	822	1			T22	1		T81	1		T7	1
valid_sources[0x56]	628	1			T11	4		T27	1		T24	4
valid_sources[0x57]	917	1			T30	1		T28	6		T29	10
valid_sources[0x58]	626	1			T70	1		T28	4		T29	8
valid_sources[0x59]	863	1			T30	1		T28	9		T29	4
valid_sources[0x5a]	843	1			T27	6		T30	1		T97	1
valid_sources[0x5b]	967	1			T30	1		T7	3		T147	2
valid_sources[0x5c]	700	1			T27	10		T24	1		T70	2
valid_sources[0x5d]	861	1			T46	2		T23	6		T24	1
valid_sources[0x5e]	978	1			T30	1		T28	9		T29	3
valid_sources[0x5f]	781	1			T7	1		T70	2		T28	8
valid_sources[0x60]	1227	1			T27	4		T30	2		T6	1
valid_sources[0x61]	790	1			T22	1		T6	1		T7	1
valid_sources[0x62]	684	1			T27	7		T28	6		T29	13
valid_sources[0x63]	916	1			T27	44		T30	1		T7	2
valid_sources[0x64]	661	1			T22	1		T27	72		T28	6
valid_sources[0x65]	830	1			T27	5		T28	9		T29	10
valid_sources[0x66]	955	1			T27	10		T81	1		T7	1
valid_sources[0x67]	637	1			T45	1		T22	2		T70	1
valid_sources[0x68]	588	1			T12	3		T24	1		T69	1
valid_sources[0x69]	738	1			T70	2		T28	19		T29	11
valid_sources[0x6a]	766	1			T82	6		T28	10		T29	10
valid_sources[0x6b]	787	1			T70	1		T28	8		T29	6
valid_sources[0x6c]	829	1			T28	6		T29	13		T137	1
valid_sources[0x6d]	824	1			T22	1		T70	1		T28	10
valid_sources[0x6e]	794	1			T22	1		T8	1		T28	8
valid_sources[0x6f]	694	1			T28	5		T29	13		T148	1
valid_sources[0x70]	642	1			T27	76		T28	11		T29	10
valid_sources[0x71]	683	1			T22	1		T27	18		T69	13
valid_sources[0x72]	787	1			T22	2		T27	168		T7	1
valid_sources[0x73]	934	1			T27	1		T28	8		T29	8
valid_sources[0x74]	868	1			T24	1		T69	6		T28	9
valid_sources[0x75]	640	1			T24	3		T70	1		T28	15
valid_sources[0x76]	1035	1			T27	1		T70	1		T28	11
valid_sources[0x77]	817	1			T21	1		T22	1		T27	3
valid_sources[0x78]	1024	1			T22	1		T70	1		T28	3
valid_sources[0x79]	844	1			T27	1		T7	1		T70	2
valid_sources[0x7a]	650	1			T22	1		T7	2		T28	9
valid_sources[0x7b]	770	1			T8	1		T82	2		T28	13
valid_sources[0x7c]	722	1			T27	3		T30	1		T28	6
valid_sources[0x7d]	590	1			T30	1		T6	1		T69	17
valid_sources[0x7e]	855	1			T48	7		T22	1		T82	4
valid_sources[0x7f]	900	1			T27	3		T7	1		T28	6
valid_sources[0x80]	680	1			T27	5		T24	1		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42216

1

T22

11

T27

806

T30

6

values[0x0]

all_enables

biggest_size

58496

1

T1

3

T3

1

T4

3

values[0x1]

all_enables

biggest_size

55431

1

T4

2

T11

1

T12

2