Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16508684

1

T2

916

T3

1511

T4

13467

full_word

152108240

1

T1

720896

T2

9108

T3

7006

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	168616584	1			T1	720896		T2	10024		T3	8517
auto[TlIntgErrCmd]	108	1			T63	7		T64	5		T65	5
auto[TlIntgErrData]	128	1			T63	7		T64	8		T65	3
auto[TlIntgErrBoth]	104	1			T63	6		T64	7		T65	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81089776

1

T1

360448

T2

4914

T3

4284

auto[1]

87527148

1

T1

360448

T2

5110

T3

4233

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8063752	1			T2	462		T3	767		T4	6728
auto[TlIntgErrNone]	partial	auto[1]	8444620	1			T2	454		T3	744		T4	6739
auto[TlIntgErrNone]	full_word	auto[0]	73025876	1			T1	360448		T2	4452		T3	3517
auto[TlIntgErrNone]	full_word	auto[1]	79082336	1			T1	360448		T2	4656		T3	3489
auto[TlIntgErrCmd]	partial	auto[0]	34	1			T63	2		T64	1		T65	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T63	5		T64	4		T65	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T124	1		T133	1		T135	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T65	2		T128	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T63	4		T64	3		T65	2
auto[TlIntgErrData]	partial	auto[1]	57	1			T63	2		T64	4		T65	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T63	1		T64	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T134	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T63	3		T64	3		T124	3
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T63	3		T64	4		T65	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T131	1		T136	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T128	2		T131	1		T126	1