Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	990888	1			T2	1348		T10	4474		T13	1683
auto[1]	10472159	1			T2	337		T3	4284		T5	4726
auto[2]	750931	1			T2	1307		T10	3301		T13	1148
auto[3]	10194269	1			T2	208		T3	4232		T5	4683

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13911831	1			T2	2469		T3	5798		T5	9409
auto[1]	2136144	1			T2	337		T3	1207		T4	4460
auto[2]	2166613	1			T2	344		T3	1251		T4	4342
auto[3]	4193659	1			T2	50		T3	260		T4	438

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9221727

1

T2

3200

T3

8516

T5

9409

auto[1]

13186520

1

T4

1

T10

34377

T11

239490

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	423888	1			T2	1104		T13	1364		T59	1
auto[0]	auto[0]	auto[1]	43714	1			T2	108		T13	142		T45	34
auto[0]	auto[0]	auto[2]	43739	1			T2	120		T13	157		T45	45
auto[0]	auto[0]	auto[3]	46286	1			T2	16		T13	20		T45	4379
auto[0]	auto[1]	auto[0]	3269624	1			T2	191		T3	2931		T5	4726
auto[0]	auto[1]	auto[1]	346825	1			T2	115		T3	586		T4	2142
auto[0]	auto[1]	auto[2]	348312	1			T2	22		T3	630		T4	2272
auto[0]	auto[1]	auto[3]	262160	1			T2	9		T3	137		T4	209
auto[0]	auto[2]	auto[0]	301894	1			T2	1088		T13	985		T45	1
auto[0]	auto[2]	auto[1]	32933	1			T2	103		T13	89		T45	395
auto[0]	auto[2]	auto[2]	33446	1			T2	108		T13	66		T45	25
auto[0]	auto[2]	auto[3]	34011	1			T2	8		T10	2		T13	8
auto[0]	auto[3]	auto[0]	3115637	1			T2	86		T3	2867		T5	4683
auto[0]	auto[3]	auto[1]	330818	1			T2	11		T3	621		T4	2318
auto[0]	auto[3]	auto[2]	348345	1			T2	94		T3	621		T4	2070
auto[0]	auto[3]	auto[3]	240095	1			T2	17		T3	123		T4	229
auto[1]	auto[0]	auto[0]	14390	1			T10	154		T111	183		T40	559
auto[1]	auto[0]	auto[1]	64592	1			T10	684		T111	760		T40	2706
auto[1]	auto[0]	auto[2]	64138	1			T10	678		T111	749		T40	2717
auto[1]	auto[0]	auto[3]	290141	1			T10	2958		T45	1		T111	3515
auto[1]	auto[1]	auto[0]	3391249	1			T10	279		T11	99521		T47	2
auto[1]	auto[1]	auto[1]	659865	1			T10	2259		T11	9129		T71	8361
auto[1]	auto[1]	auto[2]	626893	1			T10	1183		T11	9977		T71	8319
auto[1]	auto[1]	auto[3]	1567231	1			T10	10204		T11	878		T45	2
auto[1]	auto[2]	auto[0]	10456	1			T23	1		T40	481		T140	561
auto[1]	auto[2]	auto[1]	48058	1			T40	2476		T140	2511		T141	2564
auto[1]	auto[2]	auto[2]	52648	1			T10	590		T111	690		T40	1825
auto[1]	auto[2]	auto[3]	237485	1			T10	2709		T111	3242		T40	8092
auto[1]	auto[3]	auto[0]	3384693	1			T4	1		T10	111		T11	100162
auto[1]	auto[3]	auto[1]	609339	1			T10	558		T11	9966		T71	8337
auto[1]	auto[3]	auto[2]	649092	1			T10	2260		T11	8945		T71	8351
auto[1]	auto[3]	auto[3]	1516250	1			T10	9750		T11	912		T71	780