Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1234468598	228452	0	0
ctrl_regwen_rd_A	1234468598	5717	0	0
exec_rd_A	1234468598	5230	0	0
exec_regwen_rd_A	1234468598	5659	0	0
readback_rd_A	1234468598	4519	0	0
readback_regwen_rd_A	1234468598	4224	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	228452	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	5810	0	0
T28	0	4206	0	0
T29	0	4135	0	0
T30	132445	0	0	0
T38	0	1366	0	0
T50	525038	0	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T74	0	4253	0	0
T75	0	2124	0	0
T76	0	1533	0	0
T77	0	6610	0	0
T78	0	2779	0	0
T79	0	920	0	0
T80	91295	0	0	0
T81	454496	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	5717	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	467	0	0
T30	132445	0	0	0
T38	0	70	0	0
T50	525038	0	0	0
T52	0	227	0	0
T62	0	538	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T79	0	74	0	0
T80	91295	0	0	0
T81	454496	0	0	0
T118	0	176	0	0
T119	0	153	0	0
T120	0	179	0	0
T121	0	282	0	0
T122	0	153	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	5230	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	407	0	0
T30	132445	0	0	0
T38	0	94	0	0
T50	525038	0	0	0
T52	0	220	0	0
T62	0	417	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T79	0	96	0	0
T80	91295	0	0	0
T81	454496	0	0	0
T118	0	114	0	0
T119	0	92	0	0
T120	0	198	0	0
T121	0	341	0	0
T122	0	235	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	5659	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	429	0	0
T30	132445	0	0	0
T38	0	81	0	0
T50	525038	0	0	0
T52	0	234	0	0
T62	0	536	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T79	0	72	0	0
T80	91295	0	0	0
T81	454496	0	0	0
T118	0	167	0	0
T119	0	102	0	0
T120	0	140	0	0
T121	0	351	0	0
T122	0	164	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	4519	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	383	0	0
T30	132445	0	0	0
T38	0	93	0	0
T50	525038	0	0	0
T52	0	260	0	0
T62	0	525	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T79	0	30	0	0
T80	91295	0	0	0
T81	454496	0	0	0
T118	0	102	0	0
T119	0	80	0	0
T120	0	189	0	0
T121	0	325	0	0
T122	0	187	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1234468598	4224	0	0
T23	206393	0	0	0
T24	865724	0	0	0
T27	177110	370	0	0
T30	132445	0	0	0
T38	0	70	0	0
T50	525038	0	0	0
T52	0	209	0	0
T62	0	426	0	0
T71	511769	0	0	0
T72	170845	0	0	0
T73	147981	0	0	0
T79	0	61	0	0
T80	91295	0	0	0
T81	454496	0	0	0
T118	0	184	0	0
T119	0	37	0	0
T120	0	228	0	0
T121	0	286	0	0
T122	0	135	0	0