Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15632177	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

157083300

1

T1

1656

T2

1490

T3

196606

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	84937119	1			T1	16195		T2	15191		T3	65536
values[0x0]	42335937	1			T1	5264		T2	4731		T3	65805
values[0x1]	45442421	1			T1	11207		T2	10452		T3	65265

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7948602	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164766875

1

T1

14875

T2

13771

T3

196606

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	586611	1			T1	134		T2	131		T3	749
valid_sources[0x01]	578362	1			T1	144		T2	74		T3	833
valid_sources[0x02]	563147	1			T1	131		T2	76		T3	709
valid_sources[0x03]	561692	1			T1	83		T2	64		T3	819
valid_sources[0x04]	573249	1			T1	146		T2	145		T3	778
valid_sources[0x05]	594885	1			T1	134		T2	87		T3	803
valid_sources[0x06]	552986	1			T1	128		T2	71		T3	900
valid_sources[0x07]	551774	1			T1	145		T2	75		T3	730
valid_sources[0x08]	557895	1			T1	104		T2	86		T3	687
valid_sources[0x09]	577089	1			T1	122		T2	210		T3	705
valid_sources[0x0a]	581891	1			T1	121		T2	90		T3	635
valid_sources[0x0b]	565553	1			T1	108		T2	214		T3	928
valid_sources[0x0c]	559137	1			T1	116		T2	141		T3	738
valid_sources[0x0d]	595952	1			T1	111		T2	100		T3	806
valid_sources[0x0e]	679739	1			T1	125		T2	159		T3	781
valid_sources[0x0f]	559589	1			T1	120		T2	201		T3	684
valid_sources[0x10]	574482	1			T1	124		T2	47		T3	786
valid_sources[0x11]	621642	1			T1	118		T2	173		T3	699
valid_sources[0x12]	561501	1			T1	124		T2	103		T3	844
valid_sources[0x13]	560905	1			T1	120		T2	52		T3	804
valid_sources[0x14]	563273	1			T1	116		T2	88		T3	609
valid_sources[0x15]	566568	1			T1	108		T2	72		T3	672
valid_sources[0x16]	563085	1			T1	98		T2	124		T3	788
valid_sources[0x17]	557439	1			T1	127		T2	65		T3	716
valid_sources[0x18]	596066	1			T1	139		T2	134		T3	780
valid_sources[0x19]	559038	1			T1	132		T2	220		T3	783
valid_sources[0x1a]	577581	1			T1	144		T2	186		T3	817
valid_sources[0x1b]	569771	1			T1	136		T2	60		T3	808
valid_sources[0x1c]	587749	1			T1	115		T2	119		T3	723
valid_sources[0x1d]	566511	1			T1	144		T2	97		T3	762
valid_sources[0x1e]	564287	1			T1	122		T2	68		T3	767
valid_sources[0x1f]	589515	1			T1	125		T2	87		T3	825
valid_sources[0x20]	565099	1			T1	128		T2	105		T3	743
valid_sources[0x21]	572375	1			T1	147		T2	56		T3	826
valid_sources[0x22]	594991	1			T1	135		T2	86		T3	715
valid_sources[0x23]	600166	1			T1	96		T2	78		T3	749
valid_sources[0x24]	581791	1			T1	153		T2	19		T3	754
valid_sources[0x25]	557462	1			T1	127		T2	141		T3	774
valid_sources[0x26]	559965	1			T1	126		T2	125		T3	683
valid_sources[0x27]	553231	1			T1	147		T2	127		T3	704
valid_sources[0x28]	2085461	1			T1	132		T2	197		T3	740
valid_sources[0x29]	605510	1			T1	116		T2	83		T3	724
valid_sources[0x2a]	551949	1			T1	112		T2	118		T3	851
valid_sources[0x2b]	633046	1			T1	119		T2	110		T3	762
valid_sources[0x2c]	596265	1			T1	133		T2	113		T3	689
valid_sources[0x2d]	549643	1			T1	150		T2	62		T3	708
valid_sources[0x2e]	553645	1			T1	119		T2	117		T3	823
valid_sources[0x2f]	563181	1			T1	114		T2	225		T3	819
valid_sources[0x30]	554426	1			T1	110		T2	180		T3	765
valid_sources[0x31]	577341	1			T1	139		T2	129		T3	645
valid_sources[0x32]	564464	1			T1	103		T2	102		T3	761
valid_sources[0x33]	588207	1			T1	133		T2	127		T3	772
valid_sources[0x34]	567178	1			T1	142		T2	137		T3	683
valid_sources[0x35]	565181	1			T1	137		T2	114		T3	794
valid_sources[0x36]	550791	1			T1	132		T2	124		T3	810
valid_sources[0x37]	598338	1			T1	141		T2	95		T3	791
valid_sources[0x38]	562300	1			T1	159		T2	29		T3	733
valid_sources[0x39]	2090248	1			T1	130		T2	154		T3	826
valid_sources[0x3a]	562165	1			T1	123		T2	112		T3	800
valid_sources[0x3b]	553391	1			T1	119		T2	216		T3	795
valid_sources[0x3c]	579158	1			T1	126		T2	153		T3	745
valid_sources[0x3d]	554398	1			T1	91		T2	120		T3	718
valid_sources[0x3e]	570156	1			T1	122		T2	244		T3	706
valid_sources[0x3f]	633948	1			T1	93		T2	159		T3	744
valid_sources[0x40]	564833	1			T1	130		T2	98		T3	775
valid_sources[0x41]	606228	1			T1	151		T2	70		T3	788
valid_sources[0x42]	765189	1			T1	133		T2	124		T3	884
valid_sources[0x43]	563189	1			T1	135		T2	138		T3	653
valid_sources[0x44]	581973	1			T1	119		T2	214		T3	803
valid_sources[0x45]	576123	1			T1	133		T2	228		T3	668
valid_sources[0x46]	2203740	1			T1	126		T2	31		T3	816
valid_sources[0x47]	566315	1			T1	121		T2	121		T3	750
valid_sources[0x48]	620789	1			T1	116		T2	165		T3	756
valid_sources[0x49]	550338	1			T1	118		T2	113		T3	862
valid_sources[0x4a]	600314	1			T1	144		T2	202		T3	665
valid_sources[0x4b]	567700	1			T1	141		T2	118		T3	867
valid_sources[0x4c]	563765	1			T1	153		T2	142		T3	789
valid_sources[0x4d]	551595	1			T1	130		T2	218		T3	765
valid_sources[0x4e]	564133	1			T1	136		T2	143		T3	815
valid_sources[0x4f]	585289	1			T1	130		T2	128		T3	780
valid_sources[0x50]	565226	1			T1	120		T2	53		T3	763
valid_sources[0x51]	580790	1			T1	134		T2	149		T3	827
valid_sources[0x52]	601161	1			T1	115		T2	203		T3	758
valid_sources[0x53]	1315750	1			T1	97		T2	118		T3	882
valid_sources[0x54]	556368	1			T1	114		T2	113		T3	771
valid_sources[0x55]	569229	1			T1	140		T2	140		T3	928
valid_sources[0x56]	583460	1			T1	124		T2	80		T3	749
valid_sources[0x57]	566206	1			T1	128		T2	153		T3	823
valid_sources[0x58]	585952	1			T1	138		T2	141		T3	745
valid_sources[0x59]	1903011	1			T1	108		T2	79		T3	753
valid_sources[0x5a]	590263	1			T1	104		T2	85		T3	714
valid_sources[0x5b]	1776655	1			T1	146		T3	849		T4	659
valid_sources[0x5c]	554994	1			T1	125		T2	94		T3	781
valid_sources[0x5d]	585023	1			T1	125		T2	90		T3	727
valid_sources[0x5e]	612451	1			T1	131		T2	100		T3	709
valid_sources[0x5f]	562731	1			T1	109		T2	89		T3	808
valid_sources[0x60]	564597	1			T1	154		T2	82		T3	796
valid_sources[0x61]	576477	1			T1	125		T2	207		T3	769
valid_sources[0x62]	572294	1			T1	130		T2	103		T3	716
valid_sources[0x63]	592992	1			T1	121		T2	102		T3	769
valid_sources[0x64]	602810	1			T1	110		T2	105		T3	784
valid_sources[0x65]	556923	1			T1	128		T2	65		T3	688
valid_sources[0x66]	567303	1			T1	122		T2	56		T3	731
valid_sources[0x67]	575948	1			T1	137		T2	129		T3	872
valid_sources[0x68]	551614	1			T1	122		T2	80		T3	766
valid_sources[0x69]	565817	1			T1	130		T2	197		T3	880
valid_sources[0x6a]	573427	1			T1	138		T2	156		T3	869
valid_sources[0x6b]	559994	1			T1	106		T2	264		T3	852
valid_sources[0x6c]	550316	1			T1	104		T2	121		T3	757
valid_sources[0x6d]	571581	1			T1	149		T2	141		T3	725
valid_sources[0x6e]	609040	1			T1	132		T2	94		T3	650
valid_sources[0x6f]	552225	1			T1	113		T2	198		T3	803
valid_sources[0x70]	567303	1			T1	141		T2	116		T3	772
valid_sources[0x71]	552100	1			T1	122		T2	111		T3	703
valid_sources[0x72]	558854	1			T1	142		T2	98		T3	777
valid_sources[0x73]	560026	1			T1	134		T2	77		T3	853
valid_sources[0x74]	657983	1			T1	130		T2	107		T3	677
valid_sources[0x75]	569502	1			T1	162		T2	164		T3	773
valid_sources[0x76]	607181	1			T1	144		T2	139		T3	754
valid_sources[0x77]	581711	1			T1	118		T2	81		T3	782
valid_sources[0x78]	552626	1			T1	134		T2	140		T3	788
valid_sources[0x79]	594180	1			T1	147		T2	130		T3	849
valid_sources[0x7a]	573231	1			T1	121		T2	38		T3	638
valid_sources[0x7b]	578702	1			T1	145		T2	76		T3	778
valid_sources[0x7c]	565082	1			T1	128		T2	133		T3	818
valid_sources[0x7d]	560643	1			T1	127		T2	58		T3	800
valid_sources[0x7e]	573215	1			T1	109		T2	78		T3	730
valid_sources[0x7f]	583725	1			T1	120		T2	213		T3	719
valid_sources[0x80]	552565	1			T1	122		T2	63		T3	746

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77078543

1

T1

141

T2

120

T3

65536

values[0x0]

all_enables

biggest_size

40004190

1

T1

727

T2

652

T3

65805

values[0x1]

all_enables

biggest_size

40000567

1

T1

788

T2

718

T3

65265

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45707	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168203

1

T1

2

T3

100

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	58154	1			T9	275		T6	34		T27	533
values[0x0]	75373	1			T1	1		T2	2		T3	223
values[0x1]	80383	1			T1	2		T2	1		T3	198

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35218	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

178692

1

T1

2

T3

130

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	897	1			T13	1		T25	1		T23	3
valid_sources[0x01]	1004	1			T3	1		T12	1		T13	3
valid_sources[0x02]	734	1			T3	2		T7	2		T146	1
valid_sources[0x03]	840	1			T3	1		T4	1		T9	6
valid_sources[0x04]	871	1			T3	1		T12	2		T147	1
valid_sources[0x05]	1322	1			T3	3		T9	1		T12	2
valid_sources[0x06]	640	1			T3	1		T82	1		T148	1
valid_sources[0x07]	617	1			T3	3		T9	9		T12	2
valid_sources[0x08]	1010	1			T3	5		T12	2		T62	1
valid_sources[0x09]	836	1			T3	6		T9	22		T12	1
valid_sources[0x0a]	982	1			T12	4		T59	1		T22	1
valid_sources[0x0b]	617	1			T3	2		T13	1		T21	6
valid_sources[0x0c]	967	1			T3	1		T12	1		T13	1
valid_sources[0x0d]	673	1			T3	2		T9	2		T80	1
valid_sources[0x0e]	766	1			T9	13		T12	2		T62	1
valid_sources[0x0f]	1016	1			T3	1		T9	12		T12	1
valid_sources[0x10]	598	1			T20	1		T62	1		T7	1
valid_sources[0x11]	592	1			T3	2		T9	8		T12	1
valid_sources[0x12]	643	1			T3	2		T9	1		T12	2
valid_sources[0x13]	830	1			T3	1		T12	2		T149	1
valid_sources[0x14]	723	1			T20	1		T62	1		T72	8
valid_sources[0x15]	777	1			T12	3		T27	117		T150	15
valid_sources[0x16]	991	1			T3	1		T9	10		T12	2
valid_sources[0x17]	641	1			T62	1		T7	1		T25	1
valid_sources[0x18]	708	1			T9	5		T62	1		T137	4
valid_sources[0x19]	1261	1			T3	5		T9	3		T12	1
valid_sources[0x1a]	714	1			T3	3		T12	1		T61	1
valid_sources[0x1b]	1024	1			T3	1		T9	11		T12	4
valid_sources[0x1c]	1062	1			T3	2		T13	4		T62	1
valid_sources[0x1d]	723	1			T3	1		T9	12		T12	1
valid_sources[0x1e]	1271	1			T3	1		T9	12		T12	1
valid_sources[0x1f]	749	1			T3	2		T9	27		T11	4
valid_sources[0x20]	748	1			T3	1		T9	31		T13	2
valid_sources[0x21]	924	1			T3	2		T12	1		T46	2
valid_sources[0x22]	1063	1			T3	3		T12	1		T31	1
valid_sources[0x23]	932	1			T3	1		T12	2		T7	1
valid_sources[0x24]	681	1			T9	1		T12	1		T46	1
valid_sources[0x25]	655	1			T3	2		T9	9		T12	2
valid_sources[0x26]	728	1			T3	1		T62	2		T7	1
valid_sources[0x27]	800	1			T3	1		T61	7		T23	2
valid_sources[0x28]	858	1			T3	2		T12	2		T71	1
valid_sources[0x29]	662	1			T3	6		T62	1		T7	1
valid_sources[0x2a]	671	1			T12	2		T27	6		T21	3
valid_sources[0x2b]	566	1			T9	1		T12	3		T27	3
valid_sources[0x2c]	662	1			T3	2		T12	2		T62	1
valid_sources[0x2d]	821	1			T3	2		T9	15		T10	29
valid_sources[0x2e]	682	1			T3	2		T29	2		T143	1
valid_sources[0x2f]	816	1			T3	1		T12	4		T46	1
valid_sources[0x30]	744	1			T3	1		T12	1		T25	2
valid_sources[0x31]	742	1			T3	2		T12	2		T20	2
valid_sources[0x32]	911	1			T3	2		T12	1		T13	2
valid_sources[0x33]	728	1			T3	2		T60	5		T72	5
valid_sources[0x34]	857	1			T9	2		T27	3		T22	2
valid_sources[0x35]	613	1			T12	2		T62	1		T7	1
valid_sources[0x36]	892	1			T9	1		T12	1		T62	1
valid_sources[0x37]	1148	1			T3	2		T9	3		T12	2
valid_sources[0x38]	1330	1			T3	4		T9	1		T12	1
valid_sources[0x39]	1266	1			T3	3		T9	12		T62	1
valid_sources[0x3a]	1534	1			T3	2		T12	2		T27	329
valid_sources[0x3b]	770	1			T9	14		T12	1		T8	51
valid_sources[0x3c]	661	1			T3	3		T9	4		T12	1
valid_sources[0x3d]	844	1			T3	1		T12	2		T143	1
valid_sources[0x3e]	1180	1			T12	7		T27	53		T137	3
valid_sources[0x3f]	966	1			T3	2		T4	2		T9	7
valid_sources[0x40]	1008	1			T9	3		T29	155		T62	1
valid_sources[0x41]	753	1			T3	1		T9	4		T12	2
valid_sources[0x42]	694	1			T62	1		T7	2		T25	1
valid_sources[0x43]	882	1			T3	2		T12	1		T13	1
valid_sources[0x44]	758	1			T3	5		T13	1		T29	1
valid_sources[0x45]	679	1			T3	4		T12	1		T62	3
valid_sources[0x46]	642	1			T3	4		T9	7		T12	1
valid_sources[0x47]	665	1			T3	1		T12	2		T62	4
valid_sources[0x48]	588	1			T3	1		T13	1		T7	1
valid_sources[0x49]	998	1			T3	1		T9	5		T12	1
valid_sources[0x4a]	646	1			T3	2		T9	2		T13	2
valid_sources[0x4b]	857	1			T3	1		T143	1		T62	1
valid_sources[0x4c]	747	1			T3	1		T9	2		T12	1
valid_sources[0x4d]	662	1			T3	1		T9	2		T12	1
valid_sources[0x4e]	921	1			T12	2		T109	1		T22	1
valid_sources[0x4f]	762	1			T3	1		T9	3		T10	3
valid_sources[0x50]	696	1			T9	1		T12	2		T71	1
valid_sources[0x51]	744	1			T3	2		T12	1		T13	1
valid_sources[0x52]	654	1			T3	2		T12	2		T13	3
valid_sources[0x53]	711	1			T3	1		T9	8		T13	1
valid_sources[0x54]	1018	1			T3	2		T12	1		T143	1
valid_sources[0x55]	829	1			T3	4		T9	5		T27	3
valid_sources[0x56]	936	1			T3	2		T12	1		T62	2
valid_sources[0x57]	1247	1			T12	4		T27	252		T14	1
valid_sources[0x58]	982	1			T3	2		T24	2		T54	21
valid_sources[0x59]	826	1			T12	3		T7	1		T25	1
valid_sources[0x5a]	670	1			T3	2		T12	1		T21	8
valid_sources[0x5b]	646	1			T3	5		T13	4		T7	2
valid_sources[0x5c]	589	1			T3	3		T12	4		T25	1
valid_sources[0x5d]	879	1			T9	3		T12	1		T13	3
valid_sources[0x5e]	770	1			T3	1		T9	2		T12	1
valid_sources[0x5f]	869	1			T3	4		T61	6		T144	1
valid_sources[0x60]	780	1			T9	5		T12	4		T81	1
valid_sources[0x61]	953	1			T3	1		T27	4		T62	4
valid_sources[0x62]	1262	1			T12	2		T13	2		T27	151
valid_sources[0x63]	666	1			T3	1		T13	3		T25	1
valid_sources[0x64]	573	1			T3	3		T9	8		T61	3
valid_sources[0x65]	662	1			T3	6		T9	13		T12	1
valid_sources[0x66]	703	1			T12	3		T7	1		T54	26
valid_sources[0x67]	969	1			T3	4		T62	3		T146	2
valid_sources[0x68]	1136	1			T12	2		T20	2		T62	3
valid_sources[0x69]	731	1			T3	3		T61	6		T151	2
valid_sources[0x6a]	791	1			T12	1		T13	4		T62	1
valid_sources[0x6b]	809	1			T3	2		T9	2		T12	3
valid_sources[0x6c]	770	1			T9	8		T12	2		T27	2
valid_sources[0x6d]	595	1			T9	6		T13	1		T62	1
valid_sources[0x6e]	764	1			T3	3		T9	3		T10	4
valid_sources[0x6f]	784	1			T3	4		T12	2		T27	3
valid_sources[0x70]	890	1			T3	2		T9	1		T13	2
valid_sources[0x71]	1322	1			T3	3		T9	2		T12	3
valid_sources[0x72]	1075	1			T3	1		T12	2		T143	1
valid_sources[0x73]	684	1			T3	1		T9	1		T62	1
valid_sources[0x74]	666	1			T9	7		T24	2		T54	13
valid_sources[0x75]	867	1			T3	1		T13	2		T62	1
valid_sources[0x76]	700	1			T3	4		T9	1		T7	1
valid_sources[0x77]	777	1			T143	1		T62	2		T72	2
valid_sources[0x78]	809	1			T3	1		T9	2		T12	1
valid_sources[0x79]	618	1			T9	2		T12	1		T62	1
valid_sources[0x7a]	1170	1			T7	2		T25	1		T72	10
valid_sources[0x7b]	957	1			T20	1		T61	31		T72	6
valid_sources[0x7c]	989	1			T3	1		T12	1		T13	1
valid_sources[0x7d]	972	1			T3	2		T12	1		T146	1
valid_sources[0x7e]	856	1			T3	2		T9	1		T13	1
valid_sources[0x7f]	960	1			T3	2		T9	1		T62	1
valid_sources[0x80]	728	1			T3	3		T9	25		T12	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44678

1

T9

232

T6

20

T27

481

values[0x0]

all_enables

biggest_size

63232

1

T1

1

T3

71

T4

1

values[0x1]

all_enables

biggest_size

60293

1

T1

1

T3

29

T9

354