Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15553744

1

T1

31010

T2

28884

T4

147451

full_word

153932078

1

T1

1656

T2

1490

T3

196606

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169485482	1			T1	32666		T2	30374		T3	196606
auto[TlIntgErrCmd]	121	1			T68	6		T69	2		T70	5
auto[TlIntgErrData]	104	1			T68	9		T69	4		T70	8
auto[TlIntgErrBoth]	115	1			T68	5		T69	4		T70	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81595438

1

T1

16195

T2

15191

T3

65536

auto[1]

87890384

1

T1

16471

T2

15183

T3

131070

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7597792	1			T1	16054		T2	15071		T4	73785
auto[TlIntgErrNone]	partial	auto[1]	7955638	1			T1	14956		T2	13813		T4	73666
auto[TlIntgErrNone]	full_word	auto[0]	73997489	1			T1	141		T2	120		T3	65536
auto[TlIntgErrNone]	full_word	auto[1]	79934563	1			T1	1515		T2	1370		T3	131070
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T68	1		T133	2		T125	1
auto[TlIntgErrCmd]	partial	auto[1]	66	1			T68	5		T69	2		T70	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T70	1		T135	2		T126	2
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T125	1		T134	1		T135	2
auto[TlIntgErrData]	partial	auto[0]	49	1			T68	6		T70	3		T129	1
auto[TlIntgErrData]	partial	auto[1]	47	1			T68	3		T69	3		T70	4
auto[TlIntgErrData]	full_word	auto[0]	6	1			T69	1		T70	1		T131	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T127	1		T128	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T68	3		T70	3		T129	2
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T68	1		T69	4		T70	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T127	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T68	1		T131	1		T136	1