Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	864472	1			T1	938		T4	3746		T10	28
auto[1]	10495240	1			T1	2511		T4	11856		T5	217
auto[2]	664457	1			T1	632		T4	2797		T10	38
auto[3]	10194983	1			T1	2285		T4	10651		T5	207

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14394336	1			T1	11		T4	489		T5	424
auto[1]	2064749	1			T1	79		T4	2979		T10	75
auto[2]	2086185	1			T1	373		T4	4001		T10	106
auto[3]	3673882	1			T1	5903		T4	21581		T10	16

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9416832

1

T1

6366

T4

11

T5

424

auto[1]

12802320

1

T4

29039

T11

163240

T59

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	299502	1			T1	1		T10	23		T28	1585
auto[0]	auto[0]	auto[1]	31463	1			T1	9		T10	1		T28	161
auto[0]	auto[0]	auto[2]	31514	1			T1	11		T10	4		T28	156
auto[0]	auto[0]	auto[3]	51577	1			T1	917		T4	2		T28	19
auto[0]	auto[1]	auto[0]	3496114	1			T1	3		T5	217		T10	322
auto[0]	auto[1]	auto[1]	363045	1			T1	26		T4	3		T10	51
auto[0]	auto[1]	auto[2]	362765	1			T1	149		T10	21		T45	400
auto[0]	auto[1]	auto[3]	236029	1			T1	2333		T4	1		T10	3
auto[0]	auto[2]	auto[0]	214619	1			T28	1022		T143	3351		T144	2297
auto[0]	auto[2]	auto[1]	24753	1			T28	106		T143	333		T111	4
auto[0]	auto[2]	auto[2]	24505	1			T1	3		T4	1		T10	32
auto[0]	auto[2]	auto[3]	36120	1			T1	629		T4	1		T10	6
auto[0]	auto[3]	auto[0]	3327880	1			T1	7		T5	207		T10	247
auto[0]	auto[3]	auto[1]	344962	1			T1	44		T10	23		T45	377
auto[0]	auto[3]	auto[2]	359445	1			T1	210		T10	49		T45	378
auto[0]	auto[3]	auto[3]	212539	1			T1	2024		T4	3		T10	7
auto[1]	auto[0]	auto[0]	14976	1			T4	138		T59	1		T60	139
auto[1]	auto[0]	auto[1]	67077	1			T4	559		T60	615		T111	3299
auto[1]	auto[0]	auto[2]	66823	1			T4	593		T60	572		T111	3129
auto[1]	auto[0]	auto[3]	301540	1			T4	2454		T59	1		T60	2772
auto[1]	auto[1]	auto[0]	3516097	1			T4	253		T11	68058		T60	253
auto[1]	auto[1]	auto[1]	613118	1			T4	1916		T11	5902		T60	1910
auto[1]	auto[1]	auto[2]	586283	1			T4	1055		T11	7005		T60	1079
auto[1]	auto[1]	auto[3]	1321789	1			T4	8628		T11	659		T60	8710
auto[1]	auto[2]	auto[0]	11461	1			T111	655		T113	736		T145	587
auto[1]	auto[2]	auto[1]	51339	1			T111	2899		T113	3134		T145	2689
auto[1]	auto[2]	auto[2]	54578	1			T4	533		T60	587		T111	2125
auto[1]	auto[2]	auto[3]	247082	1			T4	2262		T60	2497		T111	9642
auto[1]	auto[3]	auto[0]	3513687	1			T4	98		T11	68074		T60	123
auto[1]	auto[3]	auto[1]	568992	1			T4	501		T11	6850		T60	531
auto[1]	auto[3]	auto[2]	600272	1			T4	1819		T11	6087		T60	1904
auto[1]	auto[3]	auto[3]	1267206	1			T4	8230		T11	605		T60	8303