Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1094889191	245295	0	0
ctrl_regwen_rd_A	1094889191	3798	0	0
exec_rd_A	1094889191	3340	0	0
exec_regwen_rd_A	1094889191	3666	0	0
readback_rd_A	1094889191	2514	0	0
readback_regwen_rd_A	1094889191	2233	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	245295	0	0
T9	70725	2419	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T27	0	2097	0	0
T28	955864	0	0	0
T29	0	1505	0	0
T31	33748	0	0	0
T39	0	8062	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	6366	0	0
T54	0	7237	0	0
T59	235655	0	0	0
T72	0	2587	0	0
T76	0	3745	0	0
T77	0	2524	0	0
T78	0	6570	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	3798	0	0
T9	70725	102	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T28	955864	0	0	0
T31	33748	0	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	368	0	0
T52	0	90	0	0
T59	235655	0	0	0
T72	0	219	0	0
T116	0	258	0	0
T117	0	84	0	0
T118	0	214	0	0
T119	0	61	0	0
T120	0	114	0	0
T121	0	106	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	3340	0	0
T9	70725	66	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T28	955864	0	0	0
T31	33748	0	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	308	0	0
T52	0	111	0	0
T59	235655	0	0	0
T72	0	195	0	0
T116	0	229	0	0
T117	0	77	0	0
T118	0	188	0	0
T119	0	74	0	0
T120	0	58	0	0
T121	0	150	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	3666	0	0
T9	70725	65	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T28	955864	0	0	0
T31	33748	0	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	363	0	0
T52	0	77	0	0
T59	235655	0	0	0
T72	0	190	0	0
T116	0	277	0	0
T117	0	81	0	0
T118	0	180	0	0
T119	0	43	0	0
T120	0	108	0	0
T121	0	173	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	2514	0	0
T9	70725	91	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T28	955864	0	0	0
T31	33748	0	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	374	0	0
T52	0	70	0	0
T59	235655	0	0	0
T72	0	260	0	0
T116	0	300	0	0
T117	0	47	0	0
T118	0	204	0	0
T119	0	41	0	0
T120	0	98	0	0
T121	0	155	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1094889191	2233	0	0
T9	70725	53	0	0
T10	172434	0	0	0
T11	363438	0	0	0
T12	179470	0	0	0
T13	393956	0	0	0
T28	955864	0	0	0
T31	33748	0	0	0
T45	77264	0	0	0
T50	73674	0	0	0
T51	0	308	0	0
T52	0	52	0	0
T59	235655	0	0	0
T72	0	195	0	0
T116	0	251	0	0
T117	0	63	0	0
T118	0	182	0	0
T119	0	41	0	0
T120	0	62	0	0
T121	0	139	0	0