Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15823435	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165609475

1

T1

207291

T2

98303

T3

125117

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89438904	1			T1	107148		T2	32768		T3	68653
values[0x0]	44410623	1			T1	528762		T2	32726		T3	33224
values[0x1]	47583383	1			T1	542066		T2	32809		T3	35749

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8032200	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

173400710

1

T1

210761

T2

98303

T3

131360

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	671568	1			T1	8451		T2	413		T3	475
valid_sources[0x01]	632268	1			T1	8571		T2	385		T3	489
valid_sources[0x02]	657549	1			T1	8490		T2	400		T3	502
valid_sources[0x03]	634299	1			T1	8483		T2	342		T3	521
valid_sources[0x04]	846900	1			T1	8422		T2	399		T3	570
valid_sources[0x05]	687386	1			T1	8273		T2	387		T3	571
valid_sources[0x06]	656725	1			T1	8442		T2	396		T3	537
valid_sources[0x07]	676310	1			T1	8462		T2	369		T3	469
valid_sources[0x08]	672860	1			T1	8284		T2	452		T3	608
valid_sources[0x09]	613357	1			T1	8183		T2	401		T3	494
valid_sources[0x0a]	625513	1			T1	8296		T2	357		T3	513
valid_sources[0x0b]	2076754	1			T1	8343		T2	380		T3	532
valid_sources[0x0c]	627240	1			T1	8277		T2	354		T3	536
valid_sources[0x0d]	623337	1			T1	8358		T2	472		T3	538
valid_sources[0x0e]	729502	1			T1	8290		T2	378		T3	550
valid_sources[0x0f]	638922	1			T1	8326		T2	418		T3	610
valid_sources[0x10]	645780	1			T1	8164		T2	410		T3	573
valid_sources[0x11]	635570	1			T1	8450		T2	347		T3	542
valid_sources[0x12]	669585	1			T1	8378		T2	387		T3	507
valid_sources[0x13]	718993	1			T1	8522		T2	359		T3	589
valid_sources[0x14]	636896	1			T1	8542		T2	409		T3	529
valid_sources[0x15]	642820	1			T1	8448		T2	380		T3	590
valid_sources[0x16]	663969	1			T1	8345		T2	416		T3	552
valid_sources[0x17]	655722	1			T1	8324		T2	394		T3	530
valid_sources[0x18]	651393	1			T1	8312		T2	389		T3	544
valid_sources[0x19]	632057	1			T1	8442		T2	458		T3	536
valid_sources[0x1a]	638459	1			T1	8637		T2	362		T3	551
valid_sources[0x1b]	1930726	1			T1	8409		T2	374		T3	486
valid_sources[0x1c]	619769	1			T1	8294		T2	373		T3	509
valid_sources[0x1d]	677990	1			T1	8319		T2	391		T3	536
valid_sources[0x1e]	657626	1			T1	8093		T2	323		T3	583
valid_sources[0x1f]	661457	1			T1	8543		T2	373		T3	491
valid_sources[0x20]	614474	1			T1	8359		T2	334		T3	587
valid_sources[0x21]	614413	1			T1	8366		T2	328		T3	492
valid_sources[0x22]	618748	1			T1	8504		T2	401		T3	551
valid_sources[0x23]	661778	1			T1	8495		T2	427		T3	523
valid_sources[0x24]	720374	1			T1	8296		T2	374		T3	555
valid_sources[0x25]	624363	1			T1	8144		T2	388		T3	607
valid_sources[0x26]	836193	1			T1	8383		T2	415		T3	504
valid_sources[0x27]	666884	1			T1	8291		T2	365		T3	449
valid_sources[0x28]	691716	1			T1	8462		T2	411		T3	496
valid_sources[0x29]	649839	1			T1	8442		T2	423		T3	572
valid_sources[0x2a]	1735270	1			T1	8393		T2	307		T3	646
valid_sources[0x2b]	704749	1			T1	8288		T2	382		T3	541
valid_sources[0x2c]	655652	1			T1	8264		T2	347		T3	575
valid_sources[0x2d]	711857	1			T1	8345		T2	436		T3	541
valid_sources[0x2e]	642487	1			T1	8377		T2	444		T3	520
valid_sources[0x2f]	632529	1			T1	8354		T2	394		T3	498
valid_sources[0x30]	639880	1			T1	8369		T2	351		T3	476
valid_sources[0x31]	711404	1			T1	8386		T2	380		T3	610
valid_sources[0x32]	615081	1			T1	8470		T2	398		T3	520
valid_sources[0x33]	635490	1			T1	8300		T2	361		T3	604
valid_sources[0x34]	710331	1			T1	8227		T2	401		T3	529
valid_sources[0x35]	625044	1			T1	8572		T2	337		T3	471
valid_sources[0x36]	630564	1			T1	8495		T2	425		T3	432
valid_sources[0x37]	659896	1			T1	8373		T2	358		T3	502
valid_sources[0x38]	640688	1			T1	8368		T2	385		T3	573
valid_sources[0x39]	1713728	1			T1	8285		T2	372		T3	450
valid_sources[0x3a]	631620	1			T1	8294		T2	321		T3	494
valid_sources[0x3b]	627319	1			T1	8543		T2	385		T3	620
valid_sources[0x3c]	625195	1			T1	8563		T2	457		T3	540
valid_sources[0x3d]	650518	1			T1	8592		T2	380		T3	527
valid_sources[0x3e]	663052	1			T1	8485		T2	340		T3	535
valid_sources[0x3f]	3862145	1			T1	8322		T2	406		T3	606
valid_sources[0x40]	935871	1			T1	8334		T2	361		T3	460
valid_sources[0x41]	669451	1			T1	8373		T2	421		T3	593
valid_sources[0x42]	651829	1			T1	8143		T2	418		T3	559
valid_sources[0x43]	2020444	1			T1	8292		T2	396		T3	482
valid_sources[0x44]	1899405	1			T1	8460		T2	348		T3	512
valid_sources[0x45]	628423	1			T1	8464		T2	409		T3	500
valid_sources[0x46]	623725	1			T1	8384		T2	390		T3	605
valid_sources[0x47]	633709	1			T1	8456		T2	421		T3	554
valid_sources[0x48]	619224	1			T1	8249		T2	344		T3	542
valid_sources[0x49]	616610	1			T1	8325		T2	395		T3	534
valid_sources[0x4a]	673717	1			T1	8470		T2	347		T3	491
valid_sources[0x4b]	643114	1			T1	8475		T2	421		T3	455
valid_sources[0x4c]	652898	1			T1	8354		T2	347		T3	540
valid_sources[0x4d]	632502	1			T1	8290		T2	390		T3	563
valid_sources[0x4e]	650687	1			T1	8398		T2	414		T3	542
valid_sources[0x4f]	621105	1			T1	8341		T2	386		T3	530
valid_sources[0x50]	671518	1			T1	8338		T2	377		T3	543
valid_sources[0x51]	627117	1			T1	8243		T2	337		T3	602
valid_sources[0x52]	654797	1			T1	8328		T2	421		T3	644
valid_sources[0x53]	623111	1			T1	8346		T2	382		T3	470
valid_sources[0x54]	637827	1			T1	8455		T2	486		T3	510
valid_sources[0x55]	675579	1			T1	8280		T2	456		T3	557
valid_sources[0x56]	711418	1			T1	8334		T2	401		T3	515
valid_sources[0x57]	668691	1			T1	8416		T2	412		T3	490
valid_sources[0x58]	701871	1			T1	8361		T2	359		T3	557
valid_sources[0x59]	621435	1			T1	8462		T2	337		T3	511
valid_sources[0x5a]	621420	1			T1	8307		T2	375		T3	462
valid_sources[0x5b]	679568	1			T1	8386		T2	440		T3	570
valid_sources[0x5c]	642539	1			T1	8304		T2	458		T3	549
valid_sources[0x5d]	708716	1			T1	8362		T2	396		T3	486
valid_sources[0x5e]	719891	1			T1	8289		T2	356		T3	450
valid_sources[0x5f]	617613	1			T1	8266		T2	299		T3	561
valid_sources[0x60]	624842	1			T1	8326		T2	370		T3	510
valid_sources[0x61]	639485	1			T1	8483		T2	370		T3	532
valid_sources[0x62]	646923	1			T1	8466		T2	355		T3	527
valid_sources[0x63]	684539	1			T1	8499		T2	360		T3	559
valid_sources[0x64]	642525	1			T1	8244		T2	433		T3	579
valid_sources[0x65]	626076	1			T1	8253		T2	381		T3	550
valid_sources[0x66]	642714	1			T1	8315		T2	313		T3	542
valid_sources[0x67]	649452	1			T1	8516		T2	379		T3	570
valid_sources[0x68]	642333	1			T1	8300		T2	363		T3	505
valid_sources[0x69]	664601	1			T1	8260		T2	400		T3	473
valid_sources[0x6a]	619395	1			T1	8436		T2	386		T3	497
valid_sources[0x6b]	679123	1			T1	8299		T2	313		T3	566
valid_sources[0x6c]	635137	1			T1	8456		T2	460		T3	606
valid_sources[0x6d]	623633	1			T1	8443		T2	319		T3	548
valid_sources[0x6e]	668426	1			T1	8203		T2	421		T3	525
valid_sources[0x6f]	659153	1			T1	8407		T2	354		T3	505
valid_sources[0x70]	671829	1			T1	8268		T2	406		T3	533
valid_sources[0x71]	650773	1			T1	8191		T2	336		T3	492
valid_sources[0x72]	634273	1			T1	8341		T2	384		T3	477
valid_sources[0x73]	681172	1			T1	8362		T2	338		T3	670
valid_sources[0x74]	651384	1			T1	8337		T2	319		T3	480
valid_sources[0x75]	656878	1			T1	8293		T2	386		T3	478
valid_sources[0x76]	668469	1			T1	8361		T2	418		T3	490
valid_sources[0x77]	641982	1			T1	8406		T2	371		T3	495
valid_sources[0x78]	658535	1			T1	8388		T2	347		T3	457
valid_sources[0x79]	629825	1			T1	8234		T2	392		T3	518
valid_sources[0x7a]	629727	1			T1	8445		T2	307		T3	598
valid_sources[0x7b]	674142	1			T1	8520		T2	280		T3	593
valid_sources[0x7c]	665976	1			T1	8415		T2	407		T3	585
valid_sources[0x7d]	643256	1			T1	8536		T2	453		T3	526
valid_sources[0x7e]	640142	1			T1	8340		T2	413		T3	551
valid_sources[0x7f]	655926	1			T1	8345		T2	393		T3	571
valid_sources[0x80]	1351888	1			T1	8352		T2	346		T3	598

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81495658

1

T1

103664

T2

32768

T3

62449

values[0x0]

all_enables

biggest_size

42048189

1

T1

518478

T2

32726

T3

31332

values[0x1]

all_enables

biggest_size

42065628

1

T1

517797

T2

32809

T3

31336

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

147381

1

T1

81

T2

7

T3

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51864	1			T1	39		T19	17		T20	22
values[0x0]	67204	1			T1	77		T2	21		T3	11
values[0x1]	73154	1			T1	104		T2	19		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157535

1

T1

100

T2

10

T3

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	630	1			T1	3		T23	11		T61	3
valid_sources[0x01]	739	1			T1	2		T23	14		T143	2
valid_sources[0x02]	710	1			T1	2		T8	8		T23	17
valid_sources[0x03]	675	1			T39	1		T23	15		T44	1
valid_sources[0x04]	838	1			T7	1		T23	16		T49	4
valid_sources[0x05]	701	1			T1	2		T23	16		T143	2
valid_sources[0x06]	823	1			T3	1		T19	1		T23	16
valid_sources[0x07]	909	1			T7	2		T21	75		T23	20
valid_sources[0x08]	780	1			T23	10		T49	8		T150	1
valid_sources[0x09]	663	1			T1	2		T23	12		T61	5
valid_sources[0x0a]	1120	1			T7	2		T23	14		T44	1
valid_sources[0x0b]	739	1			T1	1		T3	1		T19	3
valid_sources[0x0c]	666	1			T10	1		T39	2		T23	19
valid_sources[0x0d]	1108	1			T23	16		T44	1		T49	1
valid_sources[0x0e]	825	1			T1	2		T19	1		T23	17
valid_sources[0x0f]	597	1			T7	1		T39	1		T23	14
valid_sources[0x10]	676	1			T19	1		T7	1		T39	2
valid_sources[0x11]	797	1			T7	1		T23	15		T49	1
valid_sources[0x12]	729	1			T1	2		T39	1		T23	17
valid_sources[0x13]	554	1			T3	1		T19	1		T8	1
valid_sources[0x14]	1075	1			T23	16		T61	10		T49	7
valid_sources[0x15]	670	1			T18	3		T39	2		T23	15
valid_sources[0x16]	518	1			T39	1		T23	8		T13	1
valid_sources[0x17]	593	1			T1	1		T39	1		T23	12
valid_sources[0x18]	921	1			T23	10		T49	10		T43	2
valid_sources[0x19]	862	1			T12	3		T39	3		T23	10
valid_sources[0x1a]	807	1			T1	1		T10	1		T7	3
valid_sources[0x1b]	579	1			T1	1		T23	18		T44	2
valid_sources[0x1c]	627	1			T1	1		T39	2		T23	17
valid_sources[0x1d]	645	1			T1	1		T23	8		T151	1
valid_sources[0x1e]	516	1			T19	1		T39	1		T23	15
valid_sources[0x1f]	478	1			T1	1		T39	1		T23	12
valid_sources[0x20]	732	1			T1	1		T23	18		T143	2
valid_sources[0x21]	1184	1			T23	14		T49	1		T141	1
valid_sources[0x22]	686	1			T1	2		T19	2		T23	13
valid_sources[0x23]	650	1			T1	2		T23	10		T44	1
valid_sources[0x24]	573	1			T39	1		T23	13		T152	1
valid_sources[0x25]	1112	1			T2	2		T39	1		T23	18
valid_sources[0x26]	658	1			T1	1		T23	12		T143	4
valid_sources[0x27]	1047	1			T1	1		T8	2		T23	17
valid_sources[0x28]	669	1			T12	2		T39	1		T23	8
valid_sources[0x29]	889	1			T1	2		T23	18		T42	1
valid_sources[0x2a]	664	1			T19	2		T23	11		T150	1
valid_sources[0x2b]	1297	1			T19	1		T7	1		T23	15
valid_sources[0x2c]	734	1			T23	16		T153	1		T152	4
valid_sources[0x2d]	751	1			T1	1		T7	2		T39	2
valid_sources[0x2e]	658	1			T1	3		T19	1		T39	3
valid_sources[0x2f]	533	1			T19	1		T23	10		T44	1
valid_sources[0x30]	524	1			T1	1		T10	1		T7	1
valid_sources[0x31]	653	1			T6	2		T19	1		T7	1
valid_sources[0x32]	1136	1			T1	3		T39	1		T23	15
valid_sources[0x33]	622	1			T1	1		T19	1		T7	1
valid_sources[0x34]	1010	1			T1	3		T19	1		T41	138
valid_sources[0x35]	730	1			T1	4		T19	1		T39	2
valid_sources[0x36]	763	1			T23	11		T44	1		T13	1
valid_sources[0x37]	625	1			T1	1		T39	2		T23	13
valid_sources[0x38]	580	1			T23	11		T61	4		T49	1
valid_sources[0x39]	975	1			T1	3		T39	2		T23	17
valid_sources[0x3a]	591	1			T1	2		T12	3		T39	2
valid_sources[0x3b]	549	1			T1	1		T23	10		T44	1
valid_sources[0x3c]	1150	1			T39	2		T23	16		T143	4
valid_sources[0x3d]	779	1			T1	1		T19	1		T39	1
valid_sources[0x3e]	710	1			T23	16		T73	6		T143	1
valid_sources[0x3f]	720	1			T1	1		T7	1		T39	3
valid_sources[0x40]	583	1			T23	19		T61	2		T42	1
valid_sources[0x41]	610	1			T1	2		T39	1		T23	12
valid_sources[0x42]	671	1			T1	1		T39	1		T23	10
valid_sources[0x43]	1047	1			T1	2		T3	2		T39	1
valid_sources[0x44]	738	1			T1	1		T19	1		T39	2
valid_sources[0x45]	976	1			T1	1		T39	1		T23	7
valid_sources[0x46]	905	1			T1	2		T39	1		T23	16
valid_sources[0x47]	859	1			T18	3		T23	13		T152	1
valid_sources[0x48]	496	1			T1	3		T19	1		T39	1
valid_sources[0x49]	594	1			T7	1		T23	8		T61	3
valid_sources[0x4a]	685	1			T18	1		T39	1		T23	11
valid_sources[0x4b]	726	1			T1	2		T7	1		T39	1
valid_sources[0x4c]	659	1			T3	1		T39	2		T23	21
valid_sources[0x4d]	508	1			T1	1		T23	18		T49	3
valid_sources[0x4e]	561	1			T1	1		T19	2		T39	1
valid_sources[0x4f]	589	1			T19	1		T39	1		T23	14
valid_sources[0x50]	839	1			T83	1		T23	14		T143	3
valid_sources[0x51]	569	1			T1	2		T7	1		T23	18
valid_sources[0x52]	522	1			T1	1		T7	1		T39	2
valid_sources[0x53]	779	1			T1	2		T23	18		T143	1
valid_sources[0x54]	804	1			T18	6		T39	2		T23	10
valid_sources[0x55]	743	1			T1	2		T39	1		T23	16
valid_sources[0x56]	555	1			T5	1		T7	1		T23	15
valid_sources[0x57]	642	1			T1	1		T19	1		T23	19
valid_sources[0x58]	616	1			T1	1		T39	3		T23	14
valid_sources[0x59]	721	1			T1	1		T2	1		T39	1
valid_sources[0x5a]	777	1			T1	2		T39	2		T23	10
valid_sources[0x5b]	820	1			T19	2		T39	2		T23	13
valid_sources[0x5c]	769	1			T39	1		T23	11		T154	2
valid_sources[0x5d]	672	1			T23	14		T142	3		T152	3
valid_sources[0x5e]	505	1			T39	4		T23	15		T13	1
valid_sources[0x5f]	613	1			T1	2		T19	1		T39	2
valid_sources[0x60]	569	1			T39	1		T23	11		T44	1
valid_sources[0x61]	551	1			T1	1		T2	1		T39	1
valid_sources[0x62]	673	1			T39	1		T23	12		T143	1
valid_sources[0x63]	622	1			T1	1		T19	2		T23	22
valid_sources[0x64]	517	1			T18	3		T7	1		T39	1
valid_sources[0x65]	861	1			T23	17		T143	1		T151	1
valid_sources[0x66]	1088	1			T1	1		T23	15		T143	1
valid_sources[0x67]	1274	1			T1	2		T12	1		T23	16
valid_sources[0x68]	759	1			T39	3		T23	16		T44	2
valid_sources[0x69]	1216	1			T7	2		T23	6		T155	1
valid_sources[0x6a]	754	1			T1	1		T12	7		T19	1
valid_sources[0x6b]	714	1			T1	1		T23	12		T44	1
valid_sources[0x6c]	583	1			T39	1		T23	14		T44	1
valid_sources[0x6d]	490	1			T1	2		T23	14		T151	1
valid_sources[0x6e]	574	1			T1	1		T23	14		T151	3
valid_sources[0x6f]	782	1			T18	1		T7	2		T39	3
valid_sources[0x70]	523	1			T1	1		T23	15		T143	1
valid_sources[0x71]	798	1			T1	2		T19	1		T39	2
valid_sources[0x72]	887	1			T19	1		T7	1		T23	16
valid_sources[0x73]	540	1			T1	1		T39	3		T23	13
valid_sources[0x74]	778	1			T23	11		T44	1		T73	3
valid_sources[0x75]	689	1			T1	1		T19	1		T39	5
valid_sources[0x76]	548	1			T19	1		T39	2		T23	13
valid_sources[0x77]	841	1			T10	1		T12	1		T7	1
valid_sources[0x78]	535	1			T23	17		T49	1		T73	1
valid_sources[0x79]	848	1			T2	1		T5	1		T23	10
valid_sources[0x7a]	713	1			T1	1		T23	13		T153	1
valid_sources[0x7b]	590	1			T39	2		T23	15		T49	3
valid_sources[0x7c]	871	1			T7	1		T23	16		T44	1
valid_sources[0x7d]	939	1			T1	2		T2	4		T18	1
valid_sources[0x7e]	589	1			T6	1		T39	1		T23	19
valid_sources[0x7f]	873	1			T23	17		T142	3		T151	1
valid_sources[0x80]	1136	1			T1	1		T39	2		T8	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

39062

1

T1

18

T19

8

T20

10

values[0x0]

all_enables

biggest_size

55135

1

T1

38

T2

5

T3

2

values[0x1]

all_enables

biggest_size

53184

1

T1

25

T2

2

T3

3