Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15697393

1

T1

66701

T3

12509

T4

470

full_word

162272051

1

T1

204582

T2

98303

T3

125117

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	177969144	1			T1	211252		T2	98303		T3	137626
auto[TlIntgErrCmd]	102	1			T57	10		T58	7		T59	6
auto[TlIntgErrData]	100	1			T57	3		T58	4		T59	2
auto[TlIntgErrBoth]	98	1			T57	7		T58	9		T59	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85878402

1

T1

104240

T2

32768

T3

68653

auto[1]

92091042

1

T1

107011

T2

65535

T3

68973

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7658293	1			T1	32215		T3	6204		T4	231
auto[TlIntgErrNone]	partial	auto[1]	8038821	1			T1	34486		T3	6305		T4	239
auto[TlIntgErrNone]	full_word	auto[0]	78219982	1			T1	101019		T2	32768		T3	62449
auto[TlIntgErrNone]	full_word	auto[1]	84052048	1			T1	103563		T2	65535		T3	62668
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T57	4		T58	1		T59	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T57	5		T58	6		T59	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T133	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T57	1		T126	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	45	1			T57	2		T59	1		T126	5
auto[TlIntgErrData]	partial	auto[1]	47	1			T57	1		T58	4		T59	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T126	1		T134	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T136	1		T133	1		T137	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T57	2		T58	3		T126	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T57	4		T58	6		T59	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T57	1		T130	1		T127	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T138	1		T139	1		-	-