Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	661398	1			T20	4539		T21	5644		T40	3362
auto[1]	11534063	1			T1	131189		T3	41895		T4	1355
auto[2]	507290	1			T20	2756		T21	2616		T40	2957
auto[3]	11292000	1			T1	127451		T3	42123		T4	1324

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15009221	1			T1	214846		T3	69971		T4	1806
auto[1]	2274495	1			T1	20791		T3	6696		T4	403
auto[2]	2314308	1			T1	21009		T3	6664		T4	386
auto[3]	4396727	1			T1	1994		T3	687		T4	84

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9913920

1

T1

258636

T3

84018

T4

2679

auto[1]

14080831

1

T1

4

T6

176631

T19

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	254841	1			T20	3772		T21	4670		T40	2743
auto[0]	auto[0]	auto[1]	26354	1			T20	370		T21	472		T40	282
auto[0]	auto[0]	auto[2]	26504	1			T20	356		T21	454		T40	308
auto[0]	auto[0]	auto[3]	54088	1			T20	41		T21	47		T40	29
auto[0]	auto[1]	auto[0]	3633347	1			T1	108799		T3	34945		T4	918
auto[0]	auto[1]	auto[1]	375981	1			T1	10376		T3	3144		T4	206
auto[0]	auto[1]	auto[2]	390663	1			T1	10993		T3	3488		T4	189
auto[0]	auto[1]	auto[3]	337982	1			T1	1019		T3	318		T4	42
auto[0]	auto[2]	auto[0]	180672	1			T20	2347		T21	2189		T40	2511
auto[0]	auto[2]	auto[1]	21492	1			T20	229		T21	231		T40	250
auto[0]	auto[2]	auto[2]	23952	1			T20	168		T21	178		T40	182
auto[0]	auto[2]	auto[3]	39236	1			T20	12		T21	18		T40	14
auto[0]	auto[3]	auto[0]	3481864	1			T1	106045		T3	35026		T4	888
auto[0]	auto[3]	auto[1]	372153	1			T1	10415		T3	3552		T4	197
auto[0]	auto[3]	auto[2]	385343	1			T1	10014		T3	3176		T4	197
auto[0]	auto[3]	auto[3]	309448	1			T1	975		T3	369		T4	42
auto[1]	auto[0]	auto[0]	9856	1			T21	1		T145	399		T146	618
auto[1]	auto[0]	auto[1]	44464	1			T145	1810		T146	2712		T147	460
auto[1]	auto[0]	auto[2]	45029	1			T140	1		T145	1806		T146	2775
auto[1]	auto[0]	auto[3]	200262	1			T145	8167		T146	11974		T147	2005
auto[1]	auto[1]	auto[0]	3720580	1			T1	1		T6	73182		T19	1
auto[1]	auto[1]	auto[1]	707583	1			T6	7326		T61	1		T103	15978
auto[1]	auto[1]	auto[2]	706496	1			T1	1		T6	7232		T103	17718
auto[1]	auto[1]	auto[3]	1661431	1			T6	714		T103	72669		T104	875
auto[1]	auto[2]	auto[0]	7106	1			T145	229		T146	374		T148	2
auto[1]	auto[2]	auto[1]	31984	1			T145	1073		T146	1661		T149	3353
auto[1]	auto[2]	auto[2]	37090	1			T145	1759		T146	2515		T147	413
auto[1]	auto[2]	auto[3]	165758	1			T145	7610		T146	11713		T147	1843
auto[1]	auto[3]	auto[0]	3720955	1			T1	1		T6	72899		T72	1
auto[1]	auto[3]	auto[1]	694484	1			T6	7234		T103	17921		T104	8715
auto[1]	auto[3]	auto[2]	699231	1			T1	1		T6	7294		T103	16161
auto[1]	auto[3]	auto[3]	1628522	1			T6	750		T103	72737		T104	856