Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1127312867	220687	0	0
ctrl_regwen_rd_A	1127312867	3946	0	0
exec_rd_A	1127312867	3734	0	0
exec_regwen_rd_A	1127312867	3865	0	0
readback_rd_A	1127312867	2758	0	0
readback_regwen_rd_A	1127312867	2550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	220687	0	0
T13	1299	0	0	0
T23	159971	5984	0	0
T24	0	1880	0	0
T25	0	3507	0	0
T42	649402	0	0	0
T44	260409	0	0	0
T54	0	7404	0	0
T61	551647	0	0	0
T62	571170	0	0	0
T63	0	13175	0	0
T64	0	961	0	0
T65	0	1432	0	0
T66	0	4734	0	0
T67	0	1479	0	0
T68	0	4154	0	0
T69	75445	0	0	0
T70	72788	0	0	0
T71	436979	0	0	0
T72	301475	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	3946	0	0
T33	0	147	0	0
T45	0	537	0	0
T64	24289	91	0	0
T109	0	474	0	0
T110	0	424	0	0
T111	0	248	0	0
T112	0	263	0	0
T113	0	25	0	0
T114	0	81	0	0
T115	0	139	0	0
T116	71144	0	0	0
T117	153119	0	0	0
T118	416479	0	0	0
T119	62251	0	0	0
T120	393176	0	0	0
T121	194606	0	0	0
T122	244690	0	0	0
T123	834971	0	0	0
T124	797128	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	3734	0	0
T33	0	199	0	0
T45	0	526	0	0
T64	24289	104	0	0
T109	0	422	0	0
T110	0	374	0	0
T111	0	226	0	0
T112	0	242	0	0
T113	0	52	0	0
T114	0	105	0	0
T115	0	120	0	0
T116	71144	0	0	0
T117	153119	0	0	0
T118	416479	0	0	0
T119	62251	0	0	0
T120	393176	0	0	0
T121	194606	0	0	0
T122	244690	0	0	0
T123	834971	0	0	0
T124	797128	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	3865	0	0
T33	0	267	0	0
T45	0	495	0	0
T64	24289	101	0	0
T109	0	384	0	0
T110	0	364	0	0
T111	0	228	0	0
T112	0	257	0	0
T113	0	88	0	0
T114	0	146	0	0
T115	0	145	0	0
T116	71144	0	0	0
T117	153119	0	0	0
T118	416479	0	0	0
T119	62251	0	0	0
T120	393176	0	0	0
T121	194606	0	0	0
T122	244690	0	0	0
T123	834971	0	0	0
T124	797128	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	2758	0	0
T33	0	220	0	0
T45	0	479	0	0
T64	24289	56	0	0
T109	0	472	0	0
T110	0	415	0	0
T111	0	185	0	0
T112	0	183	0	0
T113	0	17	0	0
T114	0	60	0	0
T115	0	123	0	0
T116	71144	0	0	0
T117	153119	0	0	0
T118	416479	0	0	0
T119	62251	0	0	0
T120	393176	0	0	0
T121	194606	0	0	0
T122	244690	0	0	0
T123	834971	0	0	0
T124	797128	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1127312867	2550	0	0
T33	0	185	0	0
T45	0	555	0	0
T64	24289	82	0	0
T109	0	368	0	0
T110	0	377	0	0
T111	0	185	0	0
T112	0	146	0	0
T113	0	19	0	0
T114	0	46	0	0
T115	0	100	0	0
T116	71144	0	0	0
T117	153119	0	0	0
T118	416479	0	0	0
T119	62251	0	0	0
T120	393176	0	0	0
T121	194606	0	0	0
T122	244690	0	0	0
T123	834971	0	0	0
T124	797128	0	0	0