| T801 |
/workspace/coverage/default/32.sram_ctrl_partial_access.2475841055 |
|
|
Jul 29 06:56:58 PM PDT 24 |
Jul 29 06:57:09 PM PDT 24 |
1405123068 ps |
| T802 |
/workspace/coverage/default/17.sram_ctrl_smoke.484605844 |
|
|
Jul 29 06:53:39 PM PDT 24 |
Jul 29 06:54:00 PM PDT 24 |
2701604953 ps |
| T803 |
/workspace/coverage/default/13.sram_ctrl_regwen.363035081 |
|
|
Jul 29 06:53:10 PM PDT 24 |
Jul 29 07:07:09 PM PDT 24 |
22241310106 ps |
| T804 |
/workspace/coverage/default/23.sram_ctrl_partial_access.595960953 |
|
|
Jul 29 06:54:51 PM PDT 24 |
Jul 29 06:55:02 PM PDT 24 |
737715181 ps |
| T805 |
/workspace/coverage/default/11.sram_ctrl_mem_walk.406980860 |
|
|
Jul 29 06:53:02 PM PDT 24 |
Jul 29 06:57:57 PM PDT 24 |
5363923177 ps |
| T806 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.777578780 |
|
|
Jul 29 06:56:49 PM PDT 24 |
Jul 29 06:56:52 PM PDT 24 |
456821259 ps |
| T807 |
/workspace/coverage/default/17.sram_ctrl_stress_pipeline.1857402776 |
|
|
Jul 29 06:53:47 PM PDT 24 |
Jul 29 06:56:47 PM PDT 24 |
14947490296 ps |
| T808 |
/workspace/coverage/default/13.sram_ctrl_smoke.3576185648 |
|
|
Jul 29 06:53:09 PM PDT 24 |
Jul 29 06:54:00 PM PDT 24 |
1545908172 ps |
| T809 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.435477872 |
|
|
Jul 29 06:54:39 PM PDT 24 |
Jul 29 06:57:43 PM PDT 24 |
3069836499 ps |
| T28 |
/workspace/coverage/default/0.sram_ctrl_sec_cm.3886111485 |
|
|
Jul 29 06:52:21 PM PDT 24 |
Jul 29 06:52:24 PM PDT 24 |
344659921 ps |
| T810 |
/workspace/coverage/default/17.sram_ctrl_partial_access.1960218611 |
|
|
Jul 29 06:53:45 PM PDT 24 |
Jul 29 06:53:59 PM PDT 24 |
1535426840 ps |
| T811 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.3302705314 |
|
|
Jul 29 06:52:52 PM PDT 24 |
Jul 29 06:52:56 PM PDT 24 |
696296641 ps |
| T812 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.2900964219 |
|
|
Jul 29 06:55:37 PM PDT 24 |
Jul 29 07:03:25 PM PDT 24 |
19666724783 ps |
| T813 |
/workspace/coverage/default/22.sram_ctrl_stress_all.608303367 |
|
|
Jul 29 06:54:45 PM PDT 24 |
Jul 29 08:48:17 PM PDT 24 |
231197929472 ps |
| T814 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.4064150949 |
|
|
Jul 29 07:00:46 PM PDT 24 |
Jul 29 07:00:50 PM PDT 24 |
355291034 ps |
| T815 |
/workspace/coverage/default/37.sram_ctrl_regwen.2751852160 |
|
|
Jul 29 06:57:49 PM PDT 24 |
Jul 29 06:58:16 PM PDT 24 |
3385766005 ps |
| T816 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.4091471464 |
|
|
Jul 29 06:55:24 PM PDT 24 |
Jul 29 06:56:59 PM PDT 24 |
60493192493 ps |
| T817 |
/workspace/coverage/default/10.sram_ctrl_executable.191638170 |
|
|
Jul 29 06:52:57 PM PDT 24 |
Jul 29 07:06:36 PM PDT 24 |
45697771727 ps |
| T818 |
/workspace/coverage/default/34.sram_ctrl_executable.2697630068 |
|
|
Jul 29 06:57:19 PM PDT 24 |
Jul 29 07:14:58 PM PDT 24 |
16882583849 ps |
| T46 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3418866976 |
|
|
Jul 29 06:53:02 PM PDT 24 |
Jul 29 06:53:46 PM PDT 24 |
23360223343 ps |
| T819 |
/workspace/coverage/default/28.sram_ctrl_partial_access.520895098 |
|
|
Jul 29 06:56:08 PM PDT 24 |
Jul 29 06:56:30 PM PDT 24 |
6835460075 ps |
| T29 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1286898118 |
|
|
Jul 29 06:52:23 PM PDT 24 |
Jul 29 06:52:25 PM PDT 24 |
256633936 ps |
| T820 |
/workspace/coverage/default/36.sram_ctrl_alert_test.577992044 |
|
|
Jul 29 06:57:37 PM PDT 24 |
Jul 29 06:57:38 PM PDT 24 |
20171468 ps |
| T821 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.1522556408 |
|
|
Jul 29 06:58:17 PM PDT 24 |
Jul 29 06:59:17 PM PDT 24 |
13011766520 ps |
| T822 |
/workspace/coverage/default/21.sram_ctrl_partial_access_b2b.1108611200 |
|
|
Jul 29 06:54:25 PM PDT 24 |
Jul 29 07:00:07 PM PDT 24 |
16219910287 ps |
| T823 |
/workspace/coverage/default/24.sram_ctrl_executable.2711294431 |
|
|
Jul 29 06:55:12 PM PDT 24 |
Jul 29 07:07:14 PM PDT 24 |
16010573996 ps |
| T824 |
/workspace/coverage/default/7.sram_ctrl_executable.2609888860 |
|
|
Jul 29 06:52:40 PM PDT 24 |
Jul 29 07:12:37 PM PDT 24 |
66299218823 ps |
| T825 |
/workspace/coverage/default/33.sram_ctrl_smoke.3008140645 |
|
|
Jul 29 06:57:04 PM PDT 24 |
Jul 29 06:57:13 PM PDT 24 |
797290726 ps |
| T826 |
/workspace/coverage/default/7.sram_ctrl_regwen.3272503449 |
|
|
Jul 29 06:52:43 PM PDT 24 |
Jul 29 07:16:56 PM PDT 24 |
48288932410 ps |
| T827 |
/workspace/coverage/default/0.sram_ctrl_partial_access_b2b.2218726131 |
|
|
Jul 29 06:52:12 PM PDT 24 |
Jul 29 06:57:58 PM PDT 24 |
22496507339 ps |
| T828 |
/workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.1642611634 |
|
|
Jul 29 06:55:53 PM PDT 24 |
Jul 29 06:56:56 PM PDT 24 |
1558486133 ps |
| T829 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2949548091 |
|
|
Jul 29 06:58:09 PM PDT 24 |
Jul 29 06:59:52 PM PDT 24 |
788377950 ps |
| T830 |
/workspace/coverage/default/29.sram_ctrl_mem_walk.2994744416 |
|
|
Jul 29 06:56:20 PM PDT 24 |
Jul 29 07:01:42 PM PDT 24 |
13822529676 ps |
| T831 |
/workspace/coverage/default/25.sram_ctrl_smoke.3433313723 |
|
|
Jul 29 06:55:17 PM PDT 24 |
Jul 29 06:55:34 PM PDT 24 |
1538475406 ps |
| T832 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.316908409 |
|
|
Jul 29 06:53:20 PM PDT 24 |
Jul 29 07:16:02 PM PDT 24 |
10287773974 ps |
| T833 |
/workspace/coverage/default/31.sram_ctrl_smoke.1864807016 |
|
|
Jul 29 06:56:36 PM PDT 24 |
Jul 29 06:56:55 PM PDT 24 |
831533499 ps |
| T834 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1515719813 |
|
|
Jul 29 06:53:53 PM PDT 24 |
Jul 29 06:53:53 PM PDT 24 |
34423547 ps |
| T835 |
/workspace/coverage/default/49.sram_ctrl_stress_pipeline.2892278053 |
|
|
Jul 29 07:00:43 PM PDT 24 |
Jul 29 07:07:37 PM PDT 24 |
28484302649 ps |
| T836 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.2815645307 |
|
|
Jul 29 06:54:01 PM PDT 24 |
Jul 29 06:57:03 PM PDT 24 |
20037575502 ps |
| T837 |
/workspace/coverage/default/41.sram_ctrl_partial_access.904441482 |
|
|
Jul 29 06:58:28 PM PDT 24 |
Jul 29 06:58:48 PM PDT 24 |
2451784985 ps |
| T838 |
/workspace/coverage/default/41.sram_ctrl_smoke.4190076112 |
|
|
Jul 29 06:58:27 PM PDT 24 |
Jul 29 06:59:22 PM PDT 24 |
6087805650 ps |
| T839 |
/workspace/coverage/default/15.sram_ctrl_executable.895650537 |
|
|
Jul 29 06:53:24 PM PDT 24 |
Jul 29 07:08:27 PM PDT 24 |
53566848475 ps |
| T840 |
/workspace/coverage/default/5.sram_ctrl_partial_access.2117835746 |
|
|
Jul 29 06:52:42 PM PDT 24 |
Jul 29 06:53:07 PM PDT 24 |
587154030 ps |
| T841 |
/workspace/coverage/default/28.sram_ctrl_stress_all.4073002287 |
|
|
Jul 29 06:56:17 PM PDT 24 |
Jul 29 09:26:39 PM PDT 24 |
51710467440 ps |
| T842 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2323708692 |
|
|
Jul 29 06:54:01 PM PDT 24 |
Jul 29 06:54:09 PM PDT 24 |
2199402862 ps |
| T843 |
/workspace/coverage/default/32.sram_ctrl_smoke.1921140299 |
|
|
Jul 29 06:56:54 PM PDT 24 |
Jul 29 06:57:01 PM PDT 24 |
2777791304 ps |
| T844 |
/workspace/coverage/default/17.sram_ctrl_stress_all.2390190517 |
|
|
Jul 29 06:53:49 PM PDT 24 |
Jul 29 07:34:43 PM PDT 24 |
44781399710 ps |
| T845 |
/workspace/coverage/default/30.sram_ctrl_bijection.3349690282 |
|
|
Jul 29 06:56:29 PM PDT 24 |
Jul 29 07:10:12 PM PDT 24 |
43851153073 ps |
| T846 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.2661614732 |
|
|
Jul 29 06:58:20 PM PDT 24 |
Jul 29 06:58:58 PM PDT 24 |
742251442 ps |
| T847 |
/workspace/coverage/default/36.sram_ctrl_mem_walk.380686868 |
|
|
Jul 29 06:57:37 PM PDT 24 |
Jul 29 07:03:28 PM PDT 24 |
41394538514 ps |
| T848 |
/workspace/coverage/default/45.sram_ctrl_executable.2571952405 |
|
|
Jul 29 06:59:21 PM PDT 24 |
Jul 29 07:11:06 PM PDT 24 |
31201813747 ps |
| T849 |
/workspace/coverage/default/26.sram_ctrl_max_throughput.1841501294 |
|
|
Jul 29 06:55:37 PM PDT 24 |
Jul 29 06:57:29 PM PDT 24 |
4148563051 ps |
| T850 |
/workspace/coverage/default/9.sram_ctrl_partial_access.1168290995 |
|
|
Jul 29 06:52:52 PM PDT 24 |
Jul 29 06:53:09 PM PDT 24 |
2666347787 ps |
| T851 |
/workspace/coverage/default/21.sram_ctrl_regwen.3595337376 |
|
|
Jul 29 06:54:28 PM PDT 24 |
Jul 29 07:02:05 PM PDT 24 |
8074858696 ps |
| T115 |
/workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.1398218523 |
|
|
Jul 29 06:53:30 PM PDT 24 |
Jul 29 06:53:40 PM PDT 24 |
399110751 ps |
| T852 |
/workspace/coverage/default/24.sram_ctrl_access_during_key_req.1835804376 |
|
|
Jul 29 06:55:11 PM PDT 24 |
Jul 29 07:05:40 PM PDT 24 |
11211800355 ps |
| T853 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3578063994 |
|
|
Jul 29 06:56:16 PM PDT 24 |
Jul 29 06:56:20 PM PDT 24 |
706153410 ps |
| T854 |
/workspace/coverage/default/44.sram_ctrl_multiple_keys.3941823482 |
|
|
Jul 29 06:59:00 PM PDT 24 |
Jul 29 07:14:37 PM PDT 24 |
13459477654 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_alert_test.3033915027 |
|
|
Jul 29 06:53:19 PM PDT 24 |
Jul 29 06:53:20 PM PDT 24 |
31976925 ps |
| T856 |
/workspace/coverage/default/22.sram_ctrl_mem_partial_access.3611258320 |
|
|
Jul 29 06:54:46 PM PDT 24 |
Jul 29 06:56:23 PM PDT 24 |
20545469459 ps |
| T857 |
/workspace/coverage/default/34.sram_ctrl_access_during_key_req.286057842 |
|
|
Jul 29 06:57:16 PM PDT 24 |
Jul 29 07:07:01 PM PDT 24 |
8755010036 ps |
| T858 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.3665923959 |
|
|
Jul 29 06:59:29 PM PDT 24 |
Jul 29 06:59:33 PM PDT 24 |
349306068 ps |
| T859 |
/workspace/coverage/default/43.sram_ctrl_bijection.1330600864 |
|
|
Jul 29 06:58:48 PM PDT 24 |
Jul 29 07:31:35 PM PDT 24 |
185763500196 ps |
| T860 |
/workspace/coverage/default/6.sram_ctrl_partial_access_b2b.2926490533 |
|
|
Jul 29 06:52:40 PM PDT 24 |
Jul 29 06:59:20 PM PDT 24 |
29543816815 ps |
| T861 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2303696141 |
|
|
Jul 29 06:53:56 PM PDT 24 |
Jul 29 06:54:00 PM PDT 24 |
1522674782 ps |
| T862 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.1509855459 |
|
|
Jul 29 06:52:39 PM PDT 24 |
Jul 29 07:10:47 PM PDT 24 |
61326266962 ps |
| T863 |
/workspace/coverage/default/20.sram_ctrl_partial_access.4157591395 |
|
|
Jul 29 06:54:14 PM PDT 24 |
Jul 29 06:54:41 PM PDT 24 |
6925728012 ps |
| T864 |
/workspace/coverage/default/40.sram_ctrl_smoke.3855185040 |
|
|
Jul 29 06:58:13 PM PDT 24 |
Jul 29 07:00:32 PM PDT 24 |
1364778832 ps |
| T865 |
/workspace/coverage/default/26.sram_ctrl_partial_access.2485449980 |
|
|
Jul 29 06:55:37 PM PDT 24 |
Jul 29 06:56:12 PM PDT 24 |
1945268743 ps |
| T866 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1707438435 |
|
|
Jul 29 06:55:39 PM PDT 24 |
Jul 29 06:55:45 PM PDT 24 |
1289241903 ps |
| T867 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3106511572 |
|
|
Jul 29 06:52:19 PM PDT 24 |
Jul 29 07:11:56 PM PDT 24 |
304247337471 ps |
| T868 |
/workspace/coverage/default/12.sram_ctrl_regwen.1248477757 |
|
|
Jul 29 06:53:08 PM PDT 24 |
Jul 29 07:18:23 PM PDT 24 |
13206149218 ps |
| T869 |
/workspace/coverage/default/23.sram_ctrl_lc_escalation.1109649126 |
|
|
Jul 29 06:54:50 PM PDT 24 |
Jul 29 06:55:18 PM PDT 24 |
8535628333 ps |
| T870 |
/workspace/coverage/default/47.sram_ctrl_stress_pipeline.3242603380 |
|
|
Jul 29 07:00:09 PM PDT 24 |
Jul 29 07:05:12 PM PDT 24 |
14609647019 ps |
| T871 |
/workspace/coverage/default/16.sram_ctrl_stress_all_with_rand_reset.1417639627 |
|
|
Jul 29 06:53:34 PM PDT 24 |
Jul 29 06:55:36 PM PDT 24 |
2589240414 ps |
| T872 |
/workspace/coverage/default/40.sram_ctrl_mem_walk.3849647124 |
|
|
Jul 29 06:58:22 PM PDT 24 |
Jul 29 07:02:35 PM PDT 24 |
15762857456 ps |
| T873 |
/workspace/coverage/default/0.sram_ctrl_smoke.3466940058 |
|
|
Jul 29 06:52:15 PM PDT 24 |
Jul 29 06:52:33 PM PDT 24 |
1134129121 ps |
| T874 |
/workspace/coverage/default/29.sram_ctrl_mem_partial_access.298525934 |
|
|
Jul 29 06:56:23 PM PDT 24 |
Jul 29 06:57:38 PM PDT 24 |
961547976 ps |
| T875 |
/workspace/coverage/default/16.sram_ctrl_smoke.252488294 |
|
|
Jul 29 06:53:30 PM PDT 24 |
Jul 29 06:53:52 PM PDT 24 |
5166828683 ps |
| T876 |
/workspace/coverage/default/23.sram_ctrl_mem_partial_access.1245072424 |
|
|
Jul 29 06:54:57 PM PDT 24 |
Jul 29 06:57:02 PM PDT 24 |
7941090327 ps |
| T877 |
/workspace/coverage/default/45.sram_ctrl_stress_pipeline.3202692768 |
|
|
Jul 29 06:59:15 PM PDT 24 |
Jul 29 07:07:35 PM PDT 24 |
7376492539 ps |
| T878 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2271154527 |
|
|
Jul 29 06:56:08 PM PDT 24 |
Jul 29 07:00:00 PM PDT 24 |
13742858452 ps |
| T879 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.562394179 |
|
|
Jul 29 06:53:20 PM PDT 24 |
Jul 29 06:53:24 PM PDT 24 |
703834053 ps |
| T880 |
/workspace/coverage/default/6.sram_ctrl_executable.4033434003 |
|
|
Jul 29 06:52:41 PM PDT 24 |
Jul 29 06:55:58 PM PDT 24 |
4209149461 ps |
| T881 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3579917069 |
|
|
Jul 29 06:52:21 PM PDT 24 |
Jul 29 06:53:18 PM PDT 24 |
38351468176 ps |
| T882 |
/workspace/coverage/default/14.sram_ctrl_smoke.641204154 |
|
|
Jul 29 06:53:14 PM PDT 24 |
Jul 29 06:53:28 PM PDT 24 |
503829840 ps |
| T883 |
/workspace/coverage/default/34.sram_ctrl_stress_all.3604658922 |
|
|
Jul 29 06:57:24 PM PDT 24 |
Jul 29 08:26:34 PM PDT 24 |
142982170943 ps |
| T884 |
/workspace/coverage/default/36.sram_ctrl_stress_all.1288025795 |
|
|
Jul 29 06:57:38 PM PDT 24 |
Jul 29 07:28:06 PM PDT 24 |
113958469553 ps |
| T885 |
/workspace/coverage/default/39.sram_ctrl_stress_all.2478849628 |
|
|
Jul 29 06:58:13 PM PDT 24 |
Jul 29 07:41:51 PM PDT 24 |
86432117869 ps |
| T886 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.1355260485 |
|
|
Jul 29 06:53:20 PM PDT 24 |
Jul 29 06:56:01 PM PDT 24 |
1448959612 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.4134563956 |
|
|
Jul 29 06:57:05 PM PDT 24 |
Jul 29 06:57:27 PM PDT 24 |
1151785300 ps |
| T888 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3750413711 |
|
|
Jul 29 06:58:08 PM PDT 24 |
Jul 29 06:59:50 PM PDT 24 |
4996110509 ps |
| T889 |
/workspace/coverage/default/13.sram_ctrl_bijection.94488463 |
|
|
Jul 29 06:53:07 PM PDT 24 |
Jul 29 07:14:02 PM PDT 24 |
193058292063 ps |
| T890 |
/workspace/coverage/default/10.sram_ctrl_smoke.1838826240 |
|
|
Jul 29 06:52:52 PM PDT 24 |
Jul 29 06:53:15 PM PDT 24 |
1752660274 ps |
| T891 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.3313021977 |
|
|
Jul 29 06:52:48 PM PDT 24 |
Jul 29 06:53:58 PM PDT 24 |
822929873 ps |
| T892 |
/workspace/coverage/default/11.sram_ctrl_partial_access.3286305138 |
|
|
Jul 29 06:53:03 PM PDT 24 |
Jul 29 06:55:00 PM PDT 24 |
847872846 ps |
| T893 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.3819251276 |
|
|
Jul 29 06:58:53 PM PDT 24 |
Jul 29 07:05:12 PM PDT 24 |
60530126664 ps |
| T894 |
/workspace/coverage/default/19.sram_ctrl_regwen.3265630554 |
|
|
Jul 29 06:54:09 PM PDT 24 |
Jul 29 07:02:30 PM PDT 24 |
2084350637 ps |
| T895 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.4031067490 |
|
|
Jul 29 06:58:24 PM PDT 24 |
Jul 29 06:59:39 PM PDT 24 |
1390216417 ps |
| T896 |
/workspace/coverage/default/44.sram_ctrl_stress_all.3545796875 |
|
|
Jul 29 06:59:15 PM PDT 24 |
Jul 29 08:05:46 PM PDT 24 |
69507137519 ps |
| T897 |
/workspace/coverage/default/26.sram_ctrl_bijection.2592909857 |
|
|
Jul 29 06:55:35 PM PDT 24 |
Jul 29 07:05:12 PM PDT 24 |
31074357944 ps |
| T898 |
/workspace/coverage/default/49.sram_ctrl_smoke.704371548 |
|
|
Jul 29 07:00:42 PM PDT 24 |
Jul 29 07:02:41 PM PDT 24 |
1409674670 ps |
| T899 |
/workspace/coverage/default/25.sram_ctrl_regwen.4148318143 |
|
|
Jul 29 06:55:26 PM PDT 24 |
Jul 29 07:08:14 PM PDT 24 |
14051696801 ps |
| T900 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.1934664699 |
|
|
Jul 29 06:52:41 PM PDT 24 |
Jul 29 06:53:54 PM PDT 24 |
39819016954 ps |
| T901 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.86316668 |
|
|
Jul 29 06:54:52 PM PDT 24 |
Jul 29 07:01:58 PM PDT 24 |
17296484850 ps |
| T902 |
/workspace/coverage/default/24.sram_ctrl_bijection.4215310576 |
|
|
Jul 29 06:55:06 PM PDT 24 |
Jul 29 07:36:52 PM PDT 24 |
116252012408 ps |
| T903 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1496021869 |
|
|
Jul 29 06:58:34 PM PDT 24 |
Jul 29 07:00:45 PM PDT 24 |
15934458038 ps |
| T904 |
/workspace/coverage/default/12.sram_ctrl_ram_cfg.2133575240 |
|
|
Jul 29 06:53:08 PM PDT 24 |
Jul 29 06:53:11 PM PDT 24 |
353299201 ps |
| T905 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.1246395900 |
|
|
Jul 29 06:53:11 PM PDT 24 |
Jul 29 06:58:37 PM PDT 24 |
50925781888 ps |
| T906 |
/workspace/coverage/default/43.sram_ctrl_stress_all.3437641597 |
|
|
Jul 29 06:59:01 PM PDT 24 |
Jul 29 07:26:28 PM PDT 24 |
16465086155 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.254338569 |
|
|
Jul 29 07:00:19 PM PDT 24 |
Jul 29 07:03:26 PM PDT 24 |
19494500209 ps |
| T908 |
/workspace/coverage/default/20.sram_ctrl_stress_all.2105420059 |
|
|
Jul 29 06:54:18 PM PDT 24 |
Jul 29 08:18:40 PM PDT 24 |
80003479745 ps |
| T909 |
/workspace/coverage/default/14.sram_ctrl_stress_all.2618300166 |
|
|
Jul 29 06:53:19 PM PDT 24 |
Jul 29 08:03:35 PM PDT 24 |
144122174355 ps |
| T910 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2156063845 |
|
|
Jul 29 06:52:58 PM PDT 24 |
Jul 29 06:54:41 PM PDT 24 |
3025968940 ps |
| T911 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2562512843 |
|
|
Jul 29 06:55:22 PM PDT 24 |
Jul 29 06:55:31 PM PDT 24 |
13488217555 ps |
| T912 |
/workspace/coverage/default/49.sram_ctrl_bijection.2446751360 |
|
|
Jul 29 07:00:42 PM PDT 24 |
Jul 29 07:11:40 PM PDT 24 |
10150843915 ps |
| T913 |
/workspace/coverage/default/1.sram_ctrl_mem_walk.2141913140 |
|
|
Jul 29 06:52:18 PM PDT 24 |
Jul 29 06:55:01 PM PDT 24 |
57793654322 ps |
| T914 |
/workspace/coverage/default/37.sram_ctrl_alert_test.47661915 |
|
|
Jul 29 06:57:48 PM PDT 24 |
Jul 29 06:57:49 PM PDT 24 |
22486899 ps |
| T915 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2459389282 |
|
|
Jul 29 06:55:01 PM PDT 24 |
Jul 29 06:55:02 PM PDT 24 |
33235563 ps |
| T916 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.3778522598 |
|
|
Jul 29 06:53:08 PM PDT 24 |
Jul 29 07:17:22 PM PDT 24 |
16302586205 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_multiple_keys.3450939803 |
|
|
Jul 29 06:55:18 PM PDT 24 |
Jul 29 07:05:36 PM PDT 24 |
11988316204 ps |
| T918 |
/workspace/coverage/default/37.sram_ctrl_stress_all_with_rand_reset.120232002 |
|
|
Jul 29 06:57:49 PM PDT 24 |
Jul 29 06:58:01 PM PDT 24 |
1406486078 ps |
| T919 |
/workspace/coverage/default/15.sram_ctrl_bijection.4191229405 |
|
|
Jul 29 06:53:19 PM PDT 24 |
Jul 29 07:20:19 PM PDT 24 |
69223855950 ps |
| T920 |
/workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.1035102473 |
|
|
Jul 29 06:58:34 PM PDT 24 |
Jul 29 06:59:51 PM PDT 24 |
1932464924 ps |
| T921 |
/workspace/coverage/default/46.sram_ctrl_ram_cfg.1895801966 |
|
|
Jul 29 07:00:02 PM PDT 24 |
Jul 29 07:00:09 PM PDT 24 |
685706635 ps |
| T922 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.3448672839 |
|
|
Jul 29 06:52:46 PM PDT 24 |
Jul 29 06:53:19 PM PDT 24 |
3026830219 ps |
| T923 |
/workspace/coverage/default/19.sram_ctrl_partial_access_b2b.930639688 |
|
|
Jul 29 06:54:08 PM PDT 24 |
Jul 29 06:58:23 PM PDT 24 |
35137732158 ps |
| T924 |
/workspace/coverage/default/38.sram_ctrl_partial_access.2261866282 |
|
|
Jul 29 06:57:54 PM PDT 24 |
Jul 29 06:58:04 PM PDT 24 |
4488857094 ps |
| T925 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.3652350586 |
|
|
Jul 29 06:52:42 PM PDT 24 |
Jul 29 06:53:00 PM PDT 24 |
760651319 ps |
| T926 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.3865346234 |
|
|
Jul 29 06:52:48 PM PDT 24 |
Jul 29 06:53:19 PM PDT 24 |
21977275118 ps |
| T927 |
/workspace/coverage/default/42.sram_ctrl_ram_cfg.3545507909 |
|
|
Jul 29 06:58:48 PM PDT 24 |
Jul 29 06:58:51 PM PDT 24 |
694767543 ps |
| T928 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.4149157729 |
|
|
Jul 29 06:57:42 PM PDT 24 |
Jul 29 06:59:15 PM PDT 24 |
1569682711 ps |
| T929 |
/workspace/coverage/default/4.sram_ctrl_smoke.2393751001 |
|
|
Jul 29 06:52:38 PM PDT 24 |
Jul 29 06:53:44 PM PDT 24 |
836116676 ps |
| T930 |
/workspace/coverage/default/11.sram_ctrl_smoke.1056014634 |
|
|
Jul 29 06:53:04 PM PDT 24 |
Jul 29 06:53:29 PM PDT 24 |
6386044392 ps |
| T931 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.3425655744 |
|
|
Jul 29 06:56:42 PM PDT 24 |
Jul 29 07:02:29 PM PDT 24 |
6243383132 ps |
| T932 |
/workspace/coverage/default/24.sram_ctrl_partial_access.65105023 |
|
|
Jul 29 06:55:11 PM PDT 24 |
Jul 29 06:56:58 PM PDT 24 |
1238421108 ps |
| T933 |
/workspace/coverage/default/27.sram_ctrl_bijection.462935944 |
|
|
Jul 29 06:55:55 PM PDT 24 |
Jul 29 07:25:15 PM PDT 24 |
100998626399 ps |
| T934 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.2046456452 |
|
|
Jul 29 06:53:47 PM PDT 24 |
Jul 29 06:54:55 PM PDT 24 |
3862997888 ps |
| T935 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.972568000 |
|
|
Jul 29 06:53:35 PM PDT 24 |
Jul 29 06:54:53 PM PDT 24 |
6910917798 ps |
| T936 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2269268098 |
|
|
Jul 29 06:52:35 PM PDT 24 |
Jul 29 06:53:55 PM PDT 24 |
5810564549 ps |
| T937 |
/workspace/coverage/default/5.sram_ctrl_mem_walk.713544212 |
|
|
Jul 29 06:52:36 PM PDT 24 |
Jul 29 06:55:14 PM PDT 24 |
11918202956 ps |
| T938 |
/workspace/coverage/default/19.sram_ctrl_stress_all_with_rand_reset.1601750864 |
|
|
Jul 29 06:54:07 PM PDT 24 |
Jul 29 06:54:15 PM PDT 24 |
1060772229 ps |
| T939 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2759567420 |
|
|
Jul 29 06:54:19 PM PDT 24 |
Jul 29 06:54:50 PM PDT 24 |
4493288191 ps |
| T940 |
/workspace/coverage/default/3.sram_ctrl_regwen.1711299729 |
|
|
Jul 29 06:52:32 PM PDT 24 |
Jul 29 07:00:50 PM PDT 24 |
6060167362 ps |
| T941 |
/workspace/coverage/default/32.sram_ctrl_access_during_key_req.3783583369 |
|
|
Jul 29 06:56:58 PM PDT 24 |
Jul 29 07:12:10 PM PDT 24 |
13595326068 ps |
| T942 |
/workspace/coverage/default/30.sram_ctrl_partial_access.2809521652 |
|
|
Jul 29 06:56:30 PM PDT 24 |
Jul 29 06:56:41 PM PDT 24 |
532505494 ps |
| T943 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.3475805646 |
|
|
Jul 29 06:53:49 PM PDT 24 |
Jul 29 06:59:50 PM PDT 24 |
24253651764 ps |
| T944 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.2071721675 |
|
|
Jul 29 07:11:38 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
1448319137 ps |
| T945 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3332028563 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
1380045212 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1783503070 |
|
|
Jul 29 07:11:33 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
350024498 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3358983599 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:45 PM PDT 24 |
144237564 ps |
| T948 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.3471586985 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:40 PM PDT 24 |
517686879 ps |
| T949 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1742942283 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
77835866 ps |
| T57 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2633226749 |
|
|
Jul 29 07:11:33 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
870708106 ps |
| T60 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3389871103 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
42060520 ps |
| T950 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.2321959641 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
2422366826 ps |
| T951 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.1741045649 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:44 PM PDT 24 |
3404564599 ps |
| T58 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.700501542 |
|
|
Jul 29 07:11:44 PM PDT 24 |
Jul 29 07:11:47 PM PDT 24 |
219545536 ps |
| T74 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.1860034895 |
|
|
Jul 29 07:11:42 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
18681784 ps |
| T75 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3213808878 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:50 PM PDT 24 |
18209115 ps |
| T59 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4103053386 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
334976504 ps |
| T126 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3594156303 |
|
|
Jul 29 07:11:33 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
969834451 ps |
| T100 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1428933450 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
61309087 ps |
| T952 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3198267533 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
727810917 ps |
| T953 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2487175022 |
|
|
Jul 29 07:11:41 PM PDT 24 |
Jul 29 07:11:45 PM PDT 24 |
357014153 ps |
| T76 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.1715627304 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:12:31 PM PDT 24 |
28252002118 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3436034256 |
|
|
Jul 29 07:11:32 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
154231730 ps |
| T101 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3312782717 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
22749974 ps |
| T955 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.548710841 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:51 PM PDT 24 |
18499687 ps |
| T956 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1264075936 |
|
|
Jul 29 07:11:41 PM PDT 24 |
Jul 29 07:11:45 PM PDT 24 |
351206008 ps |
| T128 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1526602806 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:39 PM PDT 24 |
368059805 ps |
| T130 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3450520801 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
553183973 ps |
| T957 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1660081298 |
|
|
Jul 29 07:11:42 PM PDT 24 |
Jul 29 07:11:47 PM PDT 24 |
689252427 ps |
| T77 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1449240319 |
|
|
Jul 29 07:10:47 PM PDT 24 |
Jul 29 07:10:48 PM PDT 24 |
45137553 ps |
| T958 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3234739966 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
679888195 ps |
| T78 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.218559019 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
35323428 ps |
| T959 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2313372949 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
1927931658 ps |
| T107 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.3306879172 |
|
|
Jul 29 07:10:49 PM PDT 24 |
Jul 29 07:10:50 PM PDT 24 |
32344327 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.752276575 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:52 PM PDT 24 |
20114601 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3155726081 |
|
|
Jul 29 07:10:46 PM PDT 24 |
Jul 29 07:10:47 PM PDT 24 |
13355310 ps |
| T80 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2784598879 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
38576138 ps |
| T81 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1282635761 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
31167010 ps |
| T960 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3070132003 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
250895385 ps |
| T82 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.613262928 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:11:40 PM PDT 24 |
7345353663 ps |
| T961 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.3641106258 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:39 PM PDT 24 |
124935397 ps |
| T136 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.921301771 |
|
|
Jul 29 07:10:46 PM PDT 24 |
Jul 29 07:10:48 PM PDT 24 |
364201203 ps |
| T102 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.333513330 |
|
|
Jul 29 07:10:46 PM PDT 24 |
Jul 29 07:10:47 PM PDT 24 |
19897353 ps |
| T127 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.3026710153 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
306644620 ps |
| T962 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3100405335 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
16529527 ps |
| T84 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.242617403 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:12:28 PM PDT 24 |
54422854004 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1393914742 |
|
|
Jul 29 07:11:42 PM PDT 24 |
Jul 29 07:12:43 PM PDT 24 |
31985964703 ps |
| T963 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.3839671378 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
34966332 ps |
| T964 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1759093130 |
|
|
Jul 29 07:10:48 PM PDT 24 |
Jul 29 07:10:49 PM PDT 24 |
14386015 ps |
| T86 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.4264873960 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:12:32 PM PDT 24 |
14421900329 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1547345851 |
|
|
Jul 29 07:10:48 PM PDT 24 |
Jul 29 07:11:15 PM PDT 24 |
3827246513 ps |
| T965 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.2192567195 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:54 PM PDT 24 |
421945865 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.3653358469 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:11:18 PM PDT 24 |
7554316790 ps |
| T966 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.642091621 |
|
|
Jul 29 07:10:49 PM PDT 24 |
Jul 29 07:10:50 PM PDT 24 |
47809962 ps |
| T89 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.654649421 |
|
|
Jul 29 07:11:43 PM PDT 24 |
Jul 29 07:11:44 PM PDT 24 |
38895529 ps |
| T967 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1418036544 |
|
|
Jul 29 07:11:38 PM PDT 24 |
Jul 29 07:11:40 PM PDT 24 |
197999533 ps |
| T968 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1969479424 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:42 PM PDT 24 |
458726039 ps |
| T129 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.611099744 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
197087717 ps |
| T969 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1634899535 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
42419333 ps |
| T134 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1637236465 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:42 PM PDT 24 |
476161942 ps |
| T970 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1405556856 |
|
|
Jul 29 07:11:41 PM PDT 24 |
Jul 29 07:12:13 PM PDT 24 |
16790797779 ps |
| T131 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3025865857 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
480491983 ps |
| T90 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2471507056 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:12:29 PM PDT 24 |
7198781922 ps |
| T971 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.2420615067 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
22701891 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.1771260478 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
18969387 ps |
| T973 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.846885313 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:13:03 PM PDT 24 |
100687734748 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3432313866 |
|
|
Jul 29 07:11:31 PM PDT 24 |
Jul 29 07:11:32 PM PDT 24 |
36637525 ps |
| T975 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2333106023 |
|
|
Jul 29 07:11:33 PM PDT 24 |
Jul 29 07:11:34 PM PDT 24 |
22147840 ps |
| T93 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.1350624142 |
|
|
Jul 29 07:11:41 PM PDT 24 |
Jul 29 07:12:33 PM PDT 24 |
13632930019 ps |
| T94 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.225568406 |
|
|
Jul 29 07:11:32 PM PDT 24 |
Jul 29 07:11:33 PM PDT 24 |
30588857 ps |
| T95 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2755969700 |
|
|
Jul 29 07:10:49 PM PDT 24 |
Jul 29 07:11:39 PM PDT 24 |
7162662146 ps |
| T976 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3742826391 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
36682274 ps |
| T977 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3197006009 |
|
|
Jul 29 07:10:43 PM PDT 24 |
Jul 29 07:10:46 PM PDT 24 |
399780200 ps |
| T978 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.398657468 |
|
|
Jul 29 07:11:32 PM PDT 24 |
Jul 29 07:11:32 PM PDT 24 |
31453910 ps |
| T979 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.3694781492 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
23024246 ps |
| T980 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1836569726 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
45524031 ps |
| T981 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.730575668 |
|
|
Jul 29 07:10:49 PM PDT 24 |
Jul 29 07:10:50 PM PDT 24 |
12712618 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1598779821 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:39 PM PDT 24 |
580735255 ps |
| T983 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2479585226 |
|
|
Jul 29 07:11:45 PM PDT 24 |
Jul 29 07:11:46 PM PDT 24 |
14493024 ps |
| T984 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1414056077 |
|
|
Jul 29 07:11:42 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
29692054 ps |
| T132 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.2299739137 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
490421227 ps |
| T985 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3990301305 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:40 PM PDT 24 |
262100359 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3603068384 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:51 PM PDT 24 |
63202197 ps |
| T987 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.914173374 |
|
|
Jul 29 07:10:50 PM PDT 24 |
Jul 29 07:10:55 PM PDT 24 |
1445320576 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.1933689032 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
126548212 ps |
| T989 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4210360817 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
14722529 ps |
| T990 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.789320139 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:42 PM PDT 24 |
116692731 ps |
| T991 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.21053407 |
|
|
Jul 29 07:11:38 PM PDT 24 |
Jul 29 07:11:41 PM PDT 24 |
114184696 ps |
| T96 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2940019436 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:12:27 PM PDT 24 |
73715602287 ps |
| T992 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2624627037 |
|
|
Jul 29 07:10:46 PM PDT 24 |
Jul 29 07:10:49 PM PDT 24 |
523627687 ps |
| T993 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.1023312745 |
|
|
Jul 29 07:11:41 PM PDT 24 |
Jul 29 07:11:42 PM PDT 24 |
14976478 ps |
| T994 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3191875426 |
|
|
Jul 29 07:11:39 PM PDT 24 |
Jul 29 07:11:44 PM PDT 24 |
1611899107 ps |
| T995 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.2911179664 |
|
|
Jul 29 07:11:32 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
1393112940 ps |
| T996 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3626987574 |
|
|
Jul 29 07:10:48 PM PDT 24 |
Jul 29 07:10:51 PM PDT 24 |
833003172 ps |
| T997 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3137718168 |
|
|
Jul 29 07:11:38 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
2344833287 ps |
| T99 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1763961982 |
|
|
Jul 29 07:11:36 PM PDT 24 |
Jul 29 07:11:37 PM PDT 24 |
25037257 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.660506170 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
436772317 ps |
| T999 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3957139014 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:39 PM PDT 24 |
44245833 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.384703980 |
|
|
Jul 29 07:10:47 PM PDT 24 |
Jul 29 07:10:49 PM PDT 24 |
427158613 ps |
| T1001 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2688199806 |
|
|
Jul 29 07:10:47 PM PDT 24 |
Jul 29 07:10:49 PM PDT 24 |
266966346 ps |
| T133 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1641366879 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
592951429 ps |
| T1002 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2085403235 |
|
|
Jul 29 07:11:37 PM PDT 24 |
Jul 29 07:11:38 PM PDT 24 |
24242234 ps |
| T1003 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2720281580 |
|
|
Jul 29 07:11:40 PM PDT 24 |
Jul 29 07:11:43 PM PDT 24 |
78950671 ps |
| T97 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3530420640 |
|
|
Jul 29 07:11:35 PM PDT 24 |
Jul 29 07:11:36 PM PDT 24 |
59612043 ps |
| T98 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.2811912014 |
|
|
Jul 29 07:11:33 PM PDT 24 |
Jul 29 07:12:22 PM PDT 24 |
10715847561 ps |
| T1004 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3319071415 |
|
|
Jul 29 07:11:34 PM PDT 24 |
Jul 29 07:11:35 PM PDT 24 |
44926953 ps |