Summary for Variable cp_num_num_enable_bytes
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for cp_num_num_enable_bytes
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
partial |
15271213 |
1 |
|
|
T2 |
926 |
|
T3 |
108 |
|
T4 |
1165 |
full_word |
160202012 |
1 |
|
|
T2 |
9113 |
|
T3 |
1003 |
|
T4 |
5424 |
Summary for Variable cp_tl_intg_err_type
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
4 |
0 |
4 |
100.00 |
Automatically Generated Bins for cp_tl_intg_err_type
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
175472915 |
1 |
|
|
T2 |
10039 |
|
T3 |
1111 |
|
T4 |
6589 |
auto[TlIntgErrCmd] |
92 |
1 |
|
|
T68 |
2 |
|
T69 |
5 |
|
T70 |
5 |
auto[TlIntgErrData] |
105 |
1 |
|
|
T68 |
4 |
|
T69 |
3 |
|
T70 |
7 |
auto[TlIntgErrBoth] |
113 |
1 |
|
|
T68 |
4 |
|
T69 |
2 |
|
T70 |
8 |
Summary for Variable cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_write
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
84844534 |
1 |
|
|
T2 |
4975 |
|
T3 |
550 |
|
T4 |
3297 |
auto[1] |
90628691 |
1 |
|
|
T2 |
5064 |
|
T3 |
561 |
|
T4 |
3292 |
Summary for Cross cr_all
Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
16 |
0 |
16 |
100.00 |
|
Automatically Generated Cross Bins for cr_all
Bins
cp_tl_intg_err_type | cp_num_num_enable_bytes | cp_write | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[TlIntgErrNone] |
partial |
auto[0] |
7463408 |
1 |
|
|
T2 |
450 |
|
T3 |
45 |
|
T4 |
611 |
auto[TlIntgErrNone] |
partial |
auto[1] |
7807519 |
1 |
|
|
T2 |
476 |
|
T3 |
63 |
|
T4 |
554 |
auto[TlIntgErrNone] |
full_word |
auto[0] |
77380996 |
1 |
|
|
T2 |
4525 |
|
T3 |
505 |
|
T4 |
2686 |
auto[TlIntgErrNone] |
full_word |
auto[1] |
82820992 |
1 |
|
|
T2 |
4588 |
|
T3 |
498 |
|
T4 |
2738 |
auto[TlIntgErrCmd] |
partial |
auto[0] |
29 |
1 |
|
|
T68 |
2 |
|
T69 |
3 |
|
T131 |
4 |
auto[TlIntgErrCmd] |
partial |
auto[1] |
58 |
1 |
|
|
T69 |
2 |
|
T70 |
4 |
|
T130 |
3 |
auto[TlIntgErrCmd] |
full_word |
auto[0] |
1 |
1 |
|
|
T134 |
1 |
|
- |
- |
|
- |
- |
auto[TlIntgErrCmd] |
full_word |
auto[1] |
4 |
1 |
|
|
T70 |
1 |
|
T135 |
1 |
|
T136 |
1 |
auto[TlIntgErrData] |
partial |
auto[0] |
43 |
1 |
|
|
T68 |
2 |
|
T69 |
2 |
|
T70 |
3 |
auto[TlIntgErrData] |
partial |
auto[1] |
51 |
1 |
|
|
T68 |
1 |
|
T69 |
1 |
|
T70 |
3 |
auto[TlIntgErrData] |
full_word |
auto[0] |
5 |
1 |
|
|
T68 |
1 |
|
T129 |
1 |
|
T136 |
1 |
auto[TlIntgErrData] |
full_word |
auto[1] |
6 |
1 |
|
|
T70 |
1 |
|
T131 |
1 |
|
T129 |
1 |
auto[TlIntgErrBoth] |
partial |
auto[0] |
49 |
1 |
|
|
T68 |
1 |
|
T69 |
1 |
|
T70 |
2 |
auto[TlIntgErrBoth] |
partial |
auto[1] |
56 |
1 |
|
|
T68 |
3 |
|
T69 |
1 |
|
T70 |
5 |
auto[TlIntgErrBoth] |
full_word |
auto[0] |
3 |
1 |
|
|
T129 |
1 |
|
T134 |
1 |
|
T137 |
1 |
auto[TlIntgErrBoth] |
full_word |
auto[1] |
5 |
1 |
|
|
T70 |
1 |
|
T135 |
1 |
|
T136 |
1 |