Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15271213

1

T2

926

T3

108

T4

1165

full_word

160202012

1

T2

9113

T3

1003

T4

5424

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	175472915	1			T2	10039		T3	1111		T4	6589
auto[TlIntgErrCmd]	92	1			T68	2		T69	5		T70	5
auto[TlIntgErrData]	105	1			T68	4		T69	3		T70	7
auto[TlIntgErrBoth]	113	1			T68	4		T69	2		T70	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84844534

1

T2

4975

T3

550

T4

3297

auto[1]

90628691

1

T2

5064

T3

561

T4

3292

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7463408	1			T2	450		T3	45		T4	611
auto[TlIntgErrNone]	partial	auto[1]	7807519	1			T2	476		T3	63		T4	554
auto[TlIntgErrNone]	full_word	auto[0]	77380996	1			T2	4525		T3	505		T4	2686
auto[TlIntgErrNone]	full_word	auto[1]	82820992	1			T2	4588		T3	498		T4	2738
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T68	2		T69	3		T131	4
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T69	2		T70	4		T130	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T134	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T70	1		T135	1		T136	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T68	2		T69	2		T70	3
auto[TlIntgErrData]	partial	auto[1]	51	1			T68	1		T69	1		T70	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T68	1		T129	1		T136	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T70	1		T131	1		T129	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T68	1		T69	1		T70	2
auto[TlIntgErrBoth]	partial	auto[1]	56	1			T68	3		T69	1		T70	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T129	1		T134	1		T137	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T70	1		T135	1		T136	1