Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	883415	1			T5	614		T6	29		T8	5649
auto[1]	10129022	1			T2	4933		T3	18		T4	3296
auto[2]	699693	1			T5	283		T6	30		T8	3918
auto[3]	9842791	1			T2	5008		T3	11		T4	3291

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13700605	1			T2	8272		T3	23		T4	4500
auto[1]	2006735	1			T2	801		T3	5		T4	922
auto[2]	2039451	1			T2	799		T3	1		T4	972
auto[3]	3808130	1			T2	69		T4	193		T5	197

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9152600

1

T2

9941

T3

29

T4

6587

auto[1]

12402321

1

T5

1

T11

1

T41

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	328041	1			T5	499		T6	25		T8	4676
auto[0]	auto[0]	auto[1]	34342	1			T5	50		T6	3		T8	463
auto[0]	auto[0]	auto[2]	34333	1			T5	59		T6	1		T8	460
auto[0]	auto[0]	auto[3]	57185	1			T5	6		T8	50		T11	95
auto[0]	auto[1]	auto[0]	3238026	1			T2	4118		T3	15		T4	2234
auto[0]	auto[1]	auto[1]	342400	1			T2	369		T3	3		T4	451
auto[0]	auto[1]	auto[2]	352931	1			T2	413		T4	501		T5	335
auto[0]	auto[1]	auto[3]	337575	1			T2	33		T4	110		T5	67
auto[0]	auto[2]	auto[0]	255711	1			T8	3283		T11	7529		T40	7
auto[0]	auto[2]	auto[1]	29228	1			T8	346		T11	756		T40	54
auto[0]	auto[2]	auto[2]	27853	1			T5	258		T6	28		T8	271
auto[0]	auto[2]	auto[3]	44349	1			T5	25		T6	2		T8	18
auto[0]	auto[3]	auto[0]	3080150	1			T2	4154		T3	8		T4	2266
auto[0]	auto[3]	auto[1]	332898	1			T2	432		T3	2		T4	471
auto[0]	auto[3]	auto[2]	348497	1			T2	386		T3	1		T4	471
auto[0]	auto[3]	auto[3]	309081	1			T2	36		T4	83		T5	99
auto[1]	auto[0]	auto[0]	14094	1			T63	375		T111	160		T114	191
auto[1]	auto[0]	auto[1]	63602	1			T63	1652		T111	633		T114	873
auto[1]	auto[0]	auto[2]	63767	1			T63	1608		T111	645		T114	907
auto[1]	auto[0]	auto[3]	288051	1			T63	7555		T111	3024		T114	4143
auto[1]	auto[1]	auto[0]	3390536	1			T41	1		T42	1		T19	1
auto[1]	auto[1]	auto[1]	600619	1			T63	1986		T110	5176		T145	1
auto[1]	auto[1]	auto[2]	571452	1			T74	1		T63	1050		T110	5861
auto[1]	auto[1]	auto[3]	1295483	1			T41	1		T20	1		T63	8588
auto[1]	auto[2]	auto[0]	10895	1			T11	1		T55	1		T63	191
auto[1]	auto[2]	auto[1]	48091	1			T63	999		T146	810		T147	3986
auto[1]	auto[2]	auto[2]	51417	1			T63	1809		T111	582		T114	815
auto[1]	auto[2]	auto[3]	232149	1			T63	8012		T111	2683		T114	3712
auto[1]	auto[3]	auto[0]	3383152	1			T5	1		T42	1		T74	2
auto[1]	auto[3]	auto[1]	555555	1			T74	1		T63	371		T110	5823
auto[1]	auto[3]	auto[2]	589201	1			T63	2141		T110	5240		T111	1876
auto[1]	auto[3]	auto[3]	1244257	1			T56	1		T63	9415		T65	1