Line Coverage for Module :
prim_mubi8_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi8_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Module :
prim_mubi8_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
900 |
900 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1150579694 |
1150471715 |
0 |
0 |
T1 |
1142 |
1060 |
0 |
0 |
T2 |
78266 |
78195 |
0 |
0 |
T3 |
69398 |
69322 |
0 |
0 |
T4 |
74284 |
74231 |
0 |
0 |
T5 |
257037 |
257031 |
0 |
0 |
T6 |
166753 |
166746 |
0 |
0 |
T7 |
111409 |
111385 |
0 |
0 |
T8 |
204473 |
204464 |
0 |
0 |
T10 |
70273 |
70216 |
0 |
0 |
T11 |
379993 |
379982 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1150579694 |
1150457400 |
0 |
2700 |
T1 |
1142 |
1057 |
0 |
3 |
T2 |
78266 |
78192 |
0 |
3 |
T3 |
69398 |
69319 |
0 |
3 |
T4 |
74284 |
74228 |
0 |
3 |
T5 |
257037 |
257031 |
0 |
3 |
T6 |
166753 |
166746 |
0 |
3 |
T7 |
111409 |
111372 |
0 |
3 |
T8 |
204473 |
204461 |
0 |
3 |
T10 |
70273 |
70213 |
0 |
3 |
T11 |
379993 |
379981 |
0 |
3 |