Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1162977363	254094	0	0
ctrl_regwen_rd_A	1162977363	4042	0	0
exec_rd_A	1162977363	3907	0	0
exec_regwen_rd_A	1162977363	4238	0	0
readback_rd_A	1162977363	2332	0	0
readback_regwen_rd_A	1162977363	1835	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	254094	0	0
T22	95835	4235	0	0
T23	0	8454	0	0
T24	0	896	0	0
T26	34940	0	0	0
T44	263204	0	0	0
T51	0	3153	0	0
T58	0	8661	0	0
T59	0	5345	0	0
T61	71279	0	0	0
T62	780774	0	0	0
T63	133815	0	0	0
T64	163948	0	0	0
T65	82591	0	0	0
T74	606953	0	0	0
T75	0	3356	0	0
T76	0	1019	0	0
T77	0	2495	0	0
T78	0	7282	0	0
T79	528231	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	4042	0	0
T24	17126	103	0	0
T49	242482	0	0	0
T75	0	74	0	0
T95	147012	0	0	0
T111	143706	0	0	0
T115	0	124	0	0
T116	0	253	0	0
T117	0	218	0	0
T118	0	127	0	0
T119	0	400	0	0
T120	0	94	0	0
T121	0	229	0	0
T122	0	267	0	0
T123	404324	0	0	0
T124	803286	0	0	0
T125	921425	0	0	0
T126	199388	0	0	0
T127	389599	0	0	0
T128	927734	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	3907	0	0
T24	17126	81	0	0
T49	242482	0	0	0
T75	0	139	0	0
T95	147012	0	0	0
T111	143706	0	0	0
T115	0	111	0	0
T116	0	230	0	0
T117	0	232	0	0
T118	0	78	0	0
T119	0	301	0	0
T120	0	151	0	0
T121	0	244	0	0
T122	0	212	0	0
T123	404324	0	0	0
T124	803286	0	0	0
T125	921425	0	0	0
T126	199388	0	0	0
T127	389599	0	0	0
T128	927734	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	4238	0	0
T24	17126	119	0	0
T49	242482	0	0	0
T75	0	106	0	0
T95	147012	0	0	0
T111	143706	0	0	0
T115	0	149	0	0
T116	0	277	0	0
T117	0	240	0	0
T118	0	108	0	0
T119	0	478	0	0
T120	0	104	0	0
T121	0	273	0	0
T122	0	229	0	0
T123	404324	0	0	0
T124	803286	0	0	0
T125	921425	0	0	0
T126	199388	0	0	0
T127	389599	0	0	0
T128	927734	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	2332	0	0
T24	17126	86	0	0
T49	242482	0	0	0
T75	0	129	0	0
T95	147012	0	0	0
T111	143706	0	0	0
T115	0	75	0	0
T116	0	142	0	0
T117	0	295	0	0
T118	0	139	0	0
T119	0	391	0	0
T120	0	109	0	0
T121	0	276	0	0
T122	0	223	0	0
T123	404324	0	0	0
T124	803286	0	0	0
T125	921425	0	0	0
T126	199388	0	0	0
T127	389599	0	0	0
T128	927734	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162977363	1835	0	0
T24	17126	84	0	0
T49	242482	0	0	0
T75	0	73	0	0
T95	147012	0	0	0
T111	143706	0	0	0
T115	0	91	0	0
T116	0	155	0	0
T117	0	139	0	0
T118	0	59	0	0
T119	0	238	0	0
T120	0	111	0	0
T121	0	205	0	0
T122	0	177	0	0
T123	404324	0	0	0
T124	803286	0	0	0
T125	921425	0	0	0
T126	199388	0	0	0
T127	389599	0	0	0
T128	927734	0	0	0