| T793 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.270182770 |
|
|
Jul 30 06:47:05 PM PDT 24 |
Jul 30 06:47:08 PM PDT 24 |
350963820 ps |
| T794 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1749763041 |
|
|
Jul 30 06:48:55 PM PDT 24 |
Jul 30 06:50:08 PM PDT 24 |
2335018806 ps |
| T795 |
/workspace/coverage/default/37.sram_ctrl_regwen.340728086 |
|
|
Jul 30 06:49:32 PM PDT 24 |
Jul 30 07:03:05 PM PDT 24 |
37388470082 ps |
| T796 |
/workspace/coverage/default/15.sram_ctrl_smoke.1448723717 |
|
|
Jul 30 06:47:40 PM PDT 24 |
Jul 30 06:47:58 PM PDT 24 |
4209135714 ps |
| T797 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3152631549 |
|
|
Jul 30 06:51:26 PM PDT 24 |
Jul 30 06:51:27 PM PDT 24 |
44092504 ps |
| T798 |
/workspace/coverage/default/23.sram_ctrl_alert_test.2337041183 |
|
|
Jul 30 06:47:59 PM PDT 24 |
Jul 30 06:48:00 PM PDT 24 |
44464902 ps |
| T799 |
/workspace/coverage/default/20.sram_ctrl_partial_access.3654355181 |
|
|
Jul 30 06:47:51 PM PDT 24 |
Jul 30 06:48:07 PM PDT 24 |
9164869675 ps |
| T800 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.2053848975 |
|
|
Jul 30 06:49:59 PM PDT 24 |
Jul 30 06:58:58 PM PDT 24 |
140172125439 ps |
| T801 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.1333313390 |
|
|
Jul 30 06:47:53 PM PDT 24 |
Jul 30 06:47:56 PM PDT 24 |
678464569 ps |
| T802 |
/workspace/coverage/default/14.sram_ctrl_regwen.490622281 |
|
|
Jul 30 06:47:34 PM PDT 24 |
Jul 30 07:01:49 PM PDT 24 |
48822693492 ps |
| T803 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.2619899068 |
|
|
Jul 30 06:47:03 PM PDT 24 |
Jul 30 07:08:34 PM PDT 24 |
35507067363 ps |
| T804 |
/workspace/coverage/default/39.sram_ctrl_max_throughput.3706739715 |
|
|
Jul 30 06:49:48 PM PDT 24 |
Jul 30 06:51:41 PM PDT 24 |
2843235864 ps |
| T805 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.4029376697 |
|
|
Jul 30 06:49:07 PM PDT 24 |
Jul 30 07:02:43 PM PDT 24 |
43910479606 ps |
| T806 |
/workspace/coverage/default/13.sram_ctrl_bijection.3970062623 |
|
|
Jul 30 06:47:37 PM PDT 24 |
Jul 30 07:28:31 PM PDT 24 |
110532909764 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1754375728 |
|
|
Jul 30 06:47:50 PM PDT 24 |
Jul 30 06:54:49 PM PDT 24 |
75457880003 ps |
| T808 |
/workspace/coverage/default/29.sram_ctrl_partial_access_b2b.620175861 |
|
|
Jul 30 06:48:29 PM PDT 24 |
Jul 30 06:54:36 PM PDT 24 |
33561577463 ps |
| T809 |
/workspace/coverage/default/46.sram_ctrl_alert_test.1967315520 |
|
|
Jul 30 06:50:58 PM PDT 24 |
Jul 30 06:50:59 PM PDT 24 |
45184668 ps |
| T810 |
/workspace/coverage/default/48.sram_ctrl_partial_access_b2b.41277593 |
|
|
Jul 30 06:51:13 PM PDT 24 |
Jul 30 07:00:18 PM PDT 24 |
67495001826 ps |
| T811 |
/workspace/coverage/default/30.sram_ctrl_alert_test.3491859056 |
|
|
Jul 30 06:48:38 PM PDT 24 |
Jul 30 06:48:38 PM PDT 24 |
67344299 ps |
| T812 |
/workspace/coverage/default/35.sram_ctrl_alert_test.1369761828 |
|
|
Jul 30 06:49:19 PM PDT 24 |
Jul 30 06:49:19 PM PDT 24 |
18556328 ps |
| T813 |
/workspace/coverage/default/13.sram_ctrl_partial_access.1474708200 |
|
|
Jul 30 06:47:36 PM PDT 24 |
Jul 30 06:47:56 PM PDT 24 |
2191415082 ps |
| T814 |
/workspace/coverage/default/27.sram_ctrl_mem_partial_access.2119475130 |
|
|
Jul 30 06:48:18 PM PDT 24 |
Jul 30 06:50:25 PM PDT 24 |
1582437147 ps |
| T815 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2115385010 |
|
|
Jul 30 06:49:47 PM PDT 24 |
Jul 30 06:55:13 PM PDT 24 |
50368164560 ps |
| T47 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.2012823163 |
|
|
Jul 30 06:48:28 PM PDT 24 |
Jul 30 06:49:24 PM PDT 24 |
2257486902 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_alert_test.1754223978 |
|
|
Jul 30 06:47:41 PM PDT 24 |
Jul 30 06:47:42 PM PDT 24 |
18700844 ps |
| T817 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.372619802 |
|
|
Jul 30 06:47:52 PM PDT 24 |
Jul 30 06:49:04 PM PDT 24 |
4183280656 ps |
| T818 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.3678182936 |
|
|
Jul 30 06:47:06 PM PDT 24 |
Jul 30 06:48:25 PM PDT 24 |
9858885937 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_throughput_w_partial_write.408929877 |
|
|
Jul 30 06:47:46 PM PDT 24 |
Jul 30 06:47:56 PM PDT 24 |
5224464261 ps |
| T820 |
/workspace/coverage/default/15.sram_ctrl_stress_pipeline.708851887 |
|
|
Jul 30 06:47:53 PM PDT 24 |
Jul 30 06:51:49 PM PDT 24 |
16035760021 ps |
| T821 |
/workspace/coverage/default/3.sram_ctrl_alert_test.2712617870 |
|
|
Jul 30 06:47:07 PM PDT 24 |
Jul 30 06:47:08 PM PDT 24 |
16368139 ps |
| T822 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3952153354 |
|
|
Jul 30 06:46:58 PM PDT 24 |
Jul 30 06:49:54 PM PDT 24 |
10829392536 ps |
| T823 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.2020761180 |
|
|
Jul 30 06:47:09 PM PDT 24 |
Jul 30 06:49:49 PM PDT 24 |
8766232836 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.3026860761 |
|
|
Jul 30 06:48:24 PM PDT 24 |
Jul 30 06:48:27 PM PDT 24 |
717495955 ps |
| T825 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.3237640489 |
|
|
Jul 30 06:47:53 PM PDT 24 |
Jul 30 06:52:59 PM PDT 24 |
14642317857 ps |
| T826 |
/workspace/coverage/default/18.sram_ctrl_partial_access_b2b.48847111 |
|
|
Jul 30 06:47:47 PM PDT 24 |
Jul 30 06:51:34 PM PDT 24 |
22062842472 ps |
| T827 |
/workspace/coverage/default/26.sram_ctrl_partial_access.780377391 |
|
|
Jul 30 06:48:06 PM PDT 24 |
Jul 30 06:48:27 PM PDT 24 |
731176918 ps |
| T828 |
/workspace/coverage/default/45.sram_ctrl_mem_partial_access.1672607044 |
|
|
Jul 30 06:50:48 PM PDT 24 |
Jul 30 06:52:14 PM PDT 24 |
10142515627 ps |
| T829 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.578885107 |
|
|
Jul 30 06:47:16 PM PDT 24 |
Jul 30 06:49:59 PM PDT 24 |
18045072518 ps |
| T830 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.2141217717 |
|
|
Jul 30 06:47:41 PM PDT 24 |
Jul 30 06:47:44 PM PDT 24 |
598927051 ps |
| T831 |
/workspace/coverage/default/37.sram_ctrl_ram_cfg.1801234512 |
|
|
Jul 30 06:49:32 PM PDT 24 |
Jul 30 06:49:36 PM PDT 24 |
358330072 ps |
| T832 |
/workspace/coverage/default/36.sram_ctrl_regwen.3004046504 |
|
|
Jul 30 06:49:24 PM PDT 24 |
Jul 30 06:50:01 PM PDT 24 |
2007330048 ps |
| T96 |
/workspace/coverage/default/49.sram_ctrl_mem_partial_access.2756663188 |
|
|
Jul 30 06:51:32 PM PDT 24 |
Jul 30 06:53:03 PM PDT 24 |
11115147953 ps |
| T833 |
/workspace/coverage/default/25.sram_ctrl_regwen.4063376214 |
|
|
Jul 30 06:48:04 PM PDT 24 |
Jul 30 06:56:25 PM PDT 24 |
7812205934 ps |
| T834 |
/workspace/coverage/default/17.sram_ctrl_partial_access.2166570923 |
|
|
Jul 30 06:47:40 PM PDT 24 |
Jul 30 06:48:26 PM PDT 24 |
4414300308 ps |
| T835 |
/workspace/coverage/default/26.sram_ctrl_regwen.1269937443 |
|
|
Jul 30 06:48:12 PM PDT 24 |
Jul 30 06:51:17 PM PDT 24 |
4376894105 ps |
| T836 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.3692781766 |
|
|
Jul 30 06:47:31 PM PDT 24 |
Jul 30 06:53:27 PM PDT 24 |
6573416789 ps |
| T837 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.699009131 |
|
|
Jul 30 06:47:18 PM PDT 24 |
Jul 30 06:47:26 PM PDT 24 |
434588450 ps |
| T838 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.2589794686 |
|
|
Jul 30 06:49:24 PM PDT 24 |
Jul 30 06:54:28 PM PDT 24 |
16113566697 ps |
| T839 |
/workspace/coverage/default/14.sram_ctrl_access_during_key_req.3267902328 |
|
|
Jul 30 06:47:39 PM PDT 24 |
Jul 30 07:04:24 PM PDT 24 |
16700591714 ps |
| T840 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.1665597728 |
|
|
Jul 30 06:47:11 PM PDT 24 |
Jul 30 06:47:15 PM PDT 24 |
1368394871 ps |
| T841 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.4072572627 |
|
|
Jul 30 06:50:33 PM PDT 24 |
Jul 30 06:54:08 PM PDT 24 |
15732924932 ps |
| T121 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2911215898 |
|
|
Jul 30 06:50:58 PM PDT 24 |
Jul 30 06:53:41 PM PDT 24 |
1369209694 ps |
| T842 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.240940683 |
|
|
Jul 30 06:48:43 PM PDT 24 |
Jul 30 06:48:52 PM PDT 24 |
1363898908 ps |
| T843 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2191086461 |
|
|
Jul 30 06:47:43 PM PDT 24 |
Jul 30 06:47:46 PM PDT 24 |
710106911 ps |
| T844 |
/workspace/coverage/default/2.sram_ctrl_throughput_w_partial_write.2412176240 |
|
|
Jul 30 06:47:06 PM PDT 24 |
Jul 30 06:47:18 PM PDT 24 |
684650716 ps |
| T845 |
/workspace/coverage/default/20.sram_ctrl_alert_test.970496604 |
|
|
Jul 30 06:47:58 PM PDT 24 |
Jul 30 06:47:59 PM PDT 24 |
12929960 ps |
| T846 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.1334345343 |
|
|
Jul 30 06:47:55 PM PDT 24 |
Jul 30 06:48:03 PM PDT 24 |
202777112 ps |
| T847 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.1699377408 |
|
|
Jul 30 06:49:01 PM PDT 24 |
Jul 30 06:50:17 PM PDT 24 |
13152024770 ps |
| T848 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1023311676 |
|
|
Jul 30 06:48:48 PM PDT 24 |
Jul 30 08:32:08 PM PDT 24 |
183689753117 ps |
| T849 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3547709565 |
|
|
Jul 30 06:47:14 PM PDT 24 |
Jul 30 06:48:37 PM PDT 24 |
37428686821 ps |
| T850 |
/workspace/coverage/default/31.sram_ctrl_max_throughput.3646935432 |
|
|
Jul 30 06:48:37 PM PDT 24 |
Jul 30 06:49:32 PM PDT 24 |
4341705382 ps |
| T122 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.3628164176 |
|
|
Jul 30 06:47:32 PM PDT 24 |
Jul 30 06:47:53 PM PDT 24 |
4797164608 ps |
| T851 |
/workspace/coverage/default/2.sram_ctrl_lc_escalation.3092191851 |
|
|
Jul 30 06:47:09 PM PDT 24 |
Jul 30 06:47:58 PM PDT 24 |
8766593084 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_max_throughput.1743137703 |
|
|
Jul 30 06:47:34 PM PDT 24 |
Jul 30 06:48:09 PM PDT 24 |
1526703410 ps |
| T853 |
/workspace/coverage/default/7.sram_ctrl_regwen.32460845 |
|
|
Jul 30 06:47:03 PM PDT 24 |
Jul 30 06:54:26 PM PDT 24 |
5369801494 ps |
| T854 |
/workspace/coverage/default/36.sram_ctrl_partial_access.226288147 |
|
|
Jul 30 06:49:20 PM PDT 24 |
Jul 30 06:51:16 PM PDT 24 |
513683683 ps |
| T855 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.1895024563 |
|
|
Jul 30 06:47:41 PM PDT 24 |
Jul 30 07:10:59 PM PDT 24 |
84054912212 ps |
| T856 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.3416985804 |
|
|
Jul 30 06:49:28 PM PDT 24 |
Jul 30 06:50:03 PM PDT 24 |
779750503 ps |
| T857 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3752094706 |
|
|
Jul 30 06:49:35 PM PDT 24 |
Jul 30 06:59:26 PM PDT 24 |
11026383721 ps |
| T858 |
/workspace/coverage/default/49.sram_ctrl_lc_escalation.1134756094 |
|
|
Jul 30 06:51:29 PM PDT 24 |
Jul 30 06:52:08 PM PDT 24 |
16379768317 ps |
| T859 |
/workspace/coverage/default/15.sram_ctrl_access_during_key_req.3145596958 |
|
|
Jul 30 06:47:41 PM PDT 24 |
Jul 30 06:58:46 PM PDT 24 |
64957486569 ps |
| T860 |
/workspace/coverage/default/0.sram_ctrl_multiple_keys.1043988265 |
|
|
Jul 30 06:47:09 PM PDT 24 |
Jul 30 07:01:06 PM PDT 24 |
25401829202 ps |
| T861 |
/workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.1068141763 |
|
|
Jul 30 06:48:37 PM PDT 24 |
Jul 30 06:49:05 PM PDT 24 |
3330331629 ps |
| T862 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.3674815099 |
|
|
Jul 30 06:48:08 PM PDT 24 |
Jul 30 07:07:25 PM PDT 24 |
26739861141 ps |
| T863 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.2248661507 |
|
|
Jul 30 06:50:21 PM PDT 24 |
Jul 30 07:13:47 PM PDT 24 |
86098864398 ps |
| T864 |
/workspace/coverage/default/32.sram_ctrl_stress_all.784405282 |
|
|
Jul 30 06:48:51 PM PDT 24 |
Jul 30 07:18:08 PM PDT 24 |
43938425193 ps |
| T865 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.1801832205 |
|
|
Jul 30 06:51:06 PM PDT 24 |
Jul 30 07:09:01 PM PDT 24 |
40703929627 ps |
| T866 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.4061442906 |
|
|
Jul 30 06:47:49 PM PDT 24 |
Jul 30 06:47:53 PM PDT 24 |
5558761613 ps |
| T867 |
/workspace/coverage/default/15.sram_ctrl_partial_access_b2b.1112457199 |
|
|
Jul 30 06:47:45 PM PDT 24 |
Jul 30 06:53:02 PM PDT 24 |
149053736777 ps |
| T868 |
/workspace/coverage/default/41.sram_ctrl_executable.3779083830 |
|
|
Jul 30 06:50:13 PM PDT 24 |
Jul 30 06:52:17 PM PDT 24 |
13180054816 ps |
| T869 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.1993501450 |
|
|
Jul 30 06:48:24 PM PDT 24 |
Jul 30 06:51:08 PM PDT 24 |
52591141714 ps |
| T870 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2109381541 |
|
|
Jul 30 06:47:51 PM PDT 24 |
Jul 30 06:48:26 PM PDT 24 |
1384904926 ps |
| T871 |
/workspace/coverage/default/24.sram_ctrl_regwen.1024839740 |
|
|
Jul 30 06:47:53 PM PDT 24 |
Jul 30 07:04:58 PM PDT 24 |
22792368027 ps |
| T872 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.3829721752 |
|
|
Jul 30 06:50:16 PM PDT 24 |
Jul 30 06:52:40 PM PDT 24 |
5816806135 ps |
| T873 |
/workspace/coverage/default/12.sram_ctrl_regwen.3938743156 |
|
|
Jul 30 06:47:40 PM PDT 24 |
Jul 30 06:55:39 PM PDT 24 |
39986131864 ps |
| T874 |
/workspace/coverage/default/47.sram_ctrl_alert_test.3142900459 |
|
|
Jul 30 06:51:12 PM PDT 24 |
Jul 30 06:51:12 PM PDT 24 |
18969088 ps |
| T875 |
/workspace/coverage/default/49.sram_ctrl_smoke.36137994 |
|
|
Jul 30 06:51:24 PM PDT 24 |
Jul 30 06:51:30 PM PDT 24 |
1401537058 ps |
| T876 |
/workspace/coverage/default/17.sram_ctrl_executable.2362478147 |
|
|
Jul 30 06:47:48 PM PDT 24 |
Jul 30 07:01:29 PM PDT 24 |
18180923966 ps |
| T877 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.1996663145 |
|
|
Jul 30 06:47:00 PM PDT 24 |
Jul 30 06:47:04 PM PDT 24 |
515332880 ps |
| T878 |
/workspace/coverage/default/1.sram_ctrl_smoke.3439414796 |
|
|
Jul 30 06:47:03 PM PDT 24 |
Jul 30 06:47:12 PM PDT 24 |
735334963 ps |
| T879 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2848537880 |
|
|
Jul 30 06:50:44 PM PDT 24 |
Jul 30 06:57:11 PM PDT 24 |
15212968291 ps |
| T880 |
/workspace/coverage/default/48.sram_ctrl_stress_all.3564319136 |
|
|
Jul 30 06:51:25 PM PDT 24 |
Jul 30 07:49:42 PM PDT 24 |
80003428386 ps |
| T881 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.19497708 |
|
|
Jul 30 06:48:47 PM PDT 24 |
Jul 30 06:49:08 PM PDT 24 |
2025409240 ps |
| T882 |
/workspace/coverage/default/49.sram_ctrl_stress_all_with_rand_reset.3870275489 |
|
|
Jul 30 06:51:32 PM PDT 24 |
Jul 30 06:51:58 PM PDT 24 |
5823947021 ps |
| T883 |
/workspace/coverage/default/9.sram_ctrl_alert_test.760605655 |
|
|
Jul 30 06:47:24 PM PDT 24 |
Jul 30 06:47:24 PM PDT 24 |
34871670 ps |
| T884 |
/workspace/coverage/default/28.sram_ctrl_bijection.2094522031 |
|
|
Jul 30 06:48:24 PM PDT 24 |
Jul 30 07:31:12 PM PDT 24 |
547949069025 ps |
| T885 |
/workspace/coverage/default/47.sram_ctrl_smoke.755430212 |
|
|
Jul 30 06:51:02 PM PDT 24 |
Jul 30 06:51:09 PM PDT 24 |
1371591671 ps |
| T886 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.645450801 |
|
|
Jul 30 06:47:47 PM PDT 24 |
Jul 30 07:06:02 PM PDT 24 |
22712408627 ps |
| T887 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.823793319 |
|
|
Jul 30 06:51:14 PM PDT 24 |
Jul 30 06:51:55 PM PDT 24 |
27179860764 ps |
| T888 |
/workspace/coverage/default/1.sram_ctrl_regwen.827185771 |
|
|
Jul 30 06:47:13 PM PDT 24 |
Jul 30 06:50:17 PM PDT 24 |
2217815171 ps |
| T889 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.3605690463 |
|
|
Jul 30 06:48:10 PM PDT 24 |
Jul 30 06:48:50 PM PDT 24 |
2918925428 ps |
| T890 |
/workspace/coverage/default/0.sram_ctrl_executable.2452277394 |
|
|
Jul 30 06:47:03 PM PDT 24 |
Jul 30 07:04:44 PM PDT 24 |
11427492519 ps |
| T891 |
/workspace/coverage/default/5.sram_ctrl_mem_partial_access.1697430382 |
|
|
Jul 30 06:47:03 PM PDT 24 |
Jul 30 06:49:47 PM PDT 24 |
22300367255 ps |
| T892 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1045418459 |
|
|
Jul 30 06:47:48 PM PDT 24 |
Jul 30 06:56:42 PM PDT 24 |
38052386194 ps |
| T893 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2043126632 |
|
|
Jul 30 06:50:49 PM PDT 24 |
Jul 30 06:52:12 PM PDT 24 |
52292413743 ps |
| T894 |
/workspace/coverage/default/49.sram_ctrl_mem_walk.1009450323 |
|
|
Jul 30 06:51:29 PM PDT 24 |
Jul 30 06:57:14 PM PDT 24 |
37345998821 ps |
| T895 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.3467483486 |
|
|
Jul 30 06:48:03 PM PDT 24 |
Jul 30 06:53:18 PM PDT 24 |
4103323882 ps |
| T896 |
/workspace/coverage/default/18.sram_ctrl_max_throughput.1571846192 |
|
|
Jul 30 06:47:52 PM PDT 24 |
Jul 30 06:48:23 PM PDT 24 |
1468168552 ps |
| T897 |
/workspace/coverage/default/42.sram_ctrl_stress_all.78238513 |
|
|
Jul 30 06:50:23 PM PDT 24 |
Jul 30 08:51:13 PM PDT 24 |
473661442755 ps |
| T898 |
/workspace/coverage/default/42.sram_ctrl_alert_test.2135732365 |
|
|
Jul 30 06:50:24 PM PDT 24 |
Jul 30 06:50:25 PM PDT 24 |
19331012 ps |
| T899 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1061997026 |
|
|
Jul 30 06:48:45 PM PDT 24 |
Jul 30 06:50:08 PM PDT 24 |
14119811246 ps |
| T900 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.3179202102 |
|
|
Jul 30 06:47:47 PM PDT 24 |
Jul 30 06:47:50 PM PDT 24 |
350394766 ps |
| T901 |
/workspace/coverage/default/6.sram_ctrl_smoke.4056134798 |
|
|
Jul 30 06:47:21 PM PDT 24 |
Jul 30 06:47:35 PM PDT 24 |
918648184 ps |
| T902 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.4238568639 |
|
|
Jul 30 06:48:31 PM PDT 24 |
Jul 30 06:52:58 PM PDT 24 |
8044311004 ps |
| T903 |
/workspace/coverage/default/36.sram_ctrl_smoke.3865488099 |
|
|
Jul 30 06:49:22 PM PDT 24 |
Jul 30 06:49:30 PM PDT 24 |
1840075879 ps |
| T904 |
/workspace/coverage/default/17.sram_ctrl_max_throughput.95981172 |
|
|
Jul 30 06:47:43 PM PDT 24 |
Jul 30 06:48:19 PM PDT 24 |
2993026431 ps |
| T905 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.3355634710 |
|
|
Jul 30 06:49:43 PM PDT 24 |
Jul 30 06:51:13 PM PDT 24 |
3837009313 ps |
| T906 |
/workspace/coverage/default/15.sram_ctrl_executable.3626332440 |
|
|
Jul 30 06:47:50 PM PDT 24 |
Jul 30 06:50:41 PM PDT 24 |
51786851062 ps |
| T97 |
/workspace/coverage/default/8.sram_ctrl_mem_partial_access.1589590946 |
|
|
Jul 30 06:47:07 PM PDT 24 |
Jul 30 06:48:37 PM PDT 24 |
2794301105 ps |
| T907 |
/workspace/coverage/default/39.sram_ctrl_smoke.2237720468 |
|
|
Jul 30 06:49:43 PM PDT 24 |
Jul 30 06:50:02 PM PDT 24 |
9466482105 ps |
| T908 |
/workspace/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.2222925506 |
|
|
Jul 30 06:47:06 PM PDT 24 |
Jul 30 06:47:30 PM PDT 24 |
887403804 ps |
| T909 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.4230446444 |
|
|
Jul 30 06:49:37 PM PDT 24 |
Jul 30 06:52:02 PM PDT 24 |
2744993328 ps |
| T910 |
/workspace/coverage/default/26.sram_ctrl_stress_all.1862614263 |
|
|
Jul 30 06:48:11 PM PDT 24 |
Jul 30 08:20:53 PM PDT 24 |
654681507563 ps |
| T911 |
/workspace/coverage/default/47.sram_ctrl_mem_walk.2618543996 |
|
|
Jul 30 06:51:09 PM PDT 24 |
Jul 30 06:57:01 PM PDT 24 |
82617590498 ps |
| T912 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.1357951387 |
|
|
Jul 30 06:47:09 PM PDT 24 |
Jul 30 06:47:13 PM PDT 24 |
1460806814 ps |
| T913 |
/workspace/coverage/default/33.sram_ctrl_alert_test.551559692 |
|
|
Jul 30 06:48:56 PM PDT 24 |
Jul 30 06:48:56 PM PDT 24 |
17757033 ps |
| T914 |
/workspace/coverage/default/20.sram_ctrl_smoke.2785542539 |
|
|
Jul 30 06:47:51 PM PDT 24 |
Jul 30 06:48:23 PM PDT 24 |
2385794854 ps |
| T915 |
/workspace/coverage/default/11.sram_ctrl_stress_all.1876159638 |
|
|
Jul 30 06:47:36 PM PDT 24 |
Jul 30 07:13:43 PM PDT 24 |
180949588272 ps |
| T916 |
/workspace/coverage/default/30.sram_ctrl_stress_all.4012579829 |
|
|
Jul 30 06:48:38 PM PDT 24 |
Jul 30 08:45:03 PM PDT 24 |
227857958380 ps |
| T917 |
/workspace/coverage/default/45.sram_ctrl_regwen.3646073676 |
|
|
Jul 30 06:50:47 PM PDT 24 |
Jul 30 06:58:12 PM PDT 24 |
10214437547 ps |
| T918 |
/workspace/coverage/default/39.sram_ctrl_mem_walk.3295585065 |
|
|
Jul 30 06:50:00 PM PDT 24 |
Jul 30 06:56:03 PM PDT 24 |
41331191370 ps |
| T919 |
/workspace/coverage/default/19.sram_ctrl_alert_test.425294966 |
|
|
Jul 30 06:47:50 PM PDT 24 |
Jul 30 06:47:51 PM PDT 24 |
17662227 ps |
| T920 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1649296232 |
|
|
Jul 30 06:46:59 PM PDT 24 |
Jul 30 06:47:59 PM PDT 24 |
5358845276 ps |
| T921 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1376403477 |
|
|
Jul 30 06:50:45 PM PDT 24 |
Jul 30 06:53:00 PM PDT 24 |
4299744863 ps |
| T922 |
/workspace/coverage/default/36.sram_ctrl_mem_partial_access.4087729051 |
|
|
Jul 30 06:49:24 PM PDT 24 |
Jul 30 06:50:52 PM PDT 24 |
2907148699 ps |
| T923 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.510211200 |
|
|
Jul 30 06:47:52 PM PDT 24 |
Jul 30 06:48:53 PM PDT 24 |
33697028974 ps |
| T924 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.3267085765 |
|
|
Jul 30 06:47:46 PM PDT 24 |
Jul 30 07:09:19 PM PDT 24 |
39045853856 ps |
| T925 |
/workspace/coverage/default/35.sram_ctrl_stress_all.223789908 |
|
|
Jul 30 06:49:16 PM PDT 24 |
Jul 30 08:13:53 PM PDT 24 |
125587681374 ps |
| T926 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2157486624 |
|
|
Jul 30 06:47:01 PM PDT 24 |
Jul 30 06:49:07 PM PDT 24 |
11618578802 ps |
| T927 |
/workspace/coverage/default/15.sram_ctrl_partial_access.1697562254 |
|
|
Jul 30 06:47:45 PM PDT 24 |
Jul 30 06:47:55 PM PDT 24 |
3022833069 ps |
| T928 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.3257239608 |
|
|
Jul 30 06:50:19 PM PDT 24 |
Jul 30 06:50:46 PM PDT 24 |
11044444420 ps |
| T929 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.4283873563 |
|
|
Jul 30 06:50:08 PM PDT 24 |
Jul 30 06:54:11 PM PDT 24 |
18730179004 ps |
| T930 |
/workspace/coverage/default/43.sram_ctrl_mem_partial_access.2758671100 |
|
|
Jul 30 06:50:30 PM PDT 24 |
Jul 30 06:51:50 PM PDT 24 |
2689352378 ps |
| T931 |
/workspace/coverage/default/9.sram_ctrl_partial_access.2400326467 |
|
|
Jul 30 06:47:08 PM PDT 24 |
Jul 30 06:47:53 PM PDT 24 |
861787393 ps |
| T932 |
/workspace/coverage/default/18.sram_ctrl_executable.552272736 |
|
|
Jul 30 06:47:50 PM PDT 24 |
Jul 30 07:15:20 PM PDT 24 |
43264286953 ps |
| T933 |
/workspace/coverage/default/16.sram_ctrl_smoke.4231853971 |
|
|
Jul 30 06:47:48 PM PDT 24 |
Jul 30 06:47:58 PM PDT 24 |
764485228 ps |
| T934 |
/workspace/coverage/default/19.sram_ctrl_ram_cfg.1195524624 |
|
|
Jul 30 06:47:49 PM PDT 24 |
Jul 30 06:47:53 PM PDT 24 |
3738996741 ps |
| T935 |
/workspace/coverage/default/41.sram_ctrl_bijection.2877659918 |
|
|
Jul 30 06:50:09 PM PDT 24 |
Jul 30 07:11:49 PM PDT 24 |
34764365778 ps |
| T936 |
/workspace/coverage/default/20.sram_ctrl_bijection.1842784659 |
|
|
Jul 30 06:47:49 PM PDT 24 |
Jul 30 07:15:12 PM PDT 24 |
55183949168 ps |
| T937 |
/workspace/coverage/default/9.sram_ctrl_executable.1168212247 |
|
|
Jul 30 06:47:16 PM PDT 24 |
Jul 30 07:03:38 PM PDT 24 |
55257463830 ps |
| T68 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3345390328 |
|
|
Jul 30 07:23:38 PM PDT 24 |
Jul 30 07:23:39 PM PDT 24 |
344056008 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3053317612 |
|
|
Jul 30 07:23:46 PM PDT 24 |
Jul 30 07:23:47 PM PDT 24 |
185271167 ps |
| T72 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2329211066 |
|
|
Jul 30 07:23:16 PM PDT 24 |
Jul 30 07:23:17 PM PDT 24 |
41202707 ps |
| T105 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.3376444374 |
|
|
Jul 30 07:23:28 PM PDT 24 |
Jul 30 07:23:57 PM PDT 24 |
14757443710 ps |
| T938 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1235800945 |
|
|
Jul 30 07:23:33 PM PDT 24 |
Jul 30 07:23:36 PM PDT 24 |
88130255 ps |
| T106 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1816676686 |
|
|
Jul 30 07:23:17 PM PDT 24 |
Jul 30 07:23:18 PM PDT 24 |
18796883 ps |
| T939 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.2254279503 |
|
|
Jul 30 07:23:27 PM PDT 24 |
Jul 30 07:23:31 PM PDT 24 |
72845976 ps |
| T940 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3617527243 |
|
|
Jul 30 07:23:29 PM PDT 24 |
Jul 30 07:23:30 PM PDT 24 |
15933372 ps |
| T80 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.2479574967 |
|
|
Jul 30 07:23:17 PM PDT 24 |
Jul 30 07:23:18 PM PDT 24 |
15182333 ps |
| T941 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.875911106 |
|
|
Jul 30 07:23:26 PM PDT 24 |
Jul 30 07:23:28 PM PDT 24 |
22850392 ps |
| T942 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4168901636 |
|
|
Jul 30 07:23:33 PM PDT 24 |
Jul 30 07:23:37 PM PDT 24 |
2309828995 ps |
| T107 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.627053836 |
|
|
Jul 30 07:23:32 PM PDT 24 |
Jul 30 07:23:32 PM PDT 24 |
29192842 ps |
| T81 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1119310767 |
|
|
Jul 30 07:23:18 PM PDT 24 |
Jul 30 07:23:19 PM PDT 24 |
172520820 ps |
| T108 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4077814195 |
|
|
Jul 30 07:23:39 PM PDT 24 |
Jul 30 07:23:40 PM PDT 24 |
27433904 ps |
| T943 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1247220074 |
|
|
Jul 30 07:23:23 PM PDT 24 |
Jul 30 07:23:27 PM PDT 24 |
667546555 ps |
| T109 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.166617608 |
|
|
Jul 30 07:23:35 PM PDT 24 |
Jul 30 07:23:35 PM PDT 24 |
43457033 ps |
| T944 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1757344984 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
181544848 ps |
| T82 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.3728229566 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:24:32 PM PDT 24 |
14356586050 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.2505583132 |
|
|
Jul 30 07:23:16 PM PDT 24 |
Jul 30 07:23:16 PM PDT 24 |
19841889 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1982232547 |
|
|
Jul 30 07:23:36 PM PDT 24 |
Jul 30 07:23:40 PM PDT 24 |
471340386 ps |
| T946 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1613251578 |
|
|
Jul 30 07:23:48 PM PDT 24 |
Jul 30 07:23:53 PM PDT 24 |
3843366356 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3558117888 |
|
|
Jul 30 07:23:27 PM PDT 24 |
Jul 30 07:23:29 PM PDT 24 |
152795667 ps |
| T84 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.304387385 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
32829668 ps |
| T85 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3406380518 |
|
|
Jul 30 07:23:29 PM PDT 24 |
Jul 30 07:23:29 PM PDT 24 |
32366242 ps |
| T86 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.4133298345 |
|
|
Jul 30 07:23:19 PM PDT 24 |
Jul 30 07:23:20 PM PDT 24 |
258397001 ps |
| T947 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1822090414 |
|
|
Jul 30 07:23:16 PM PDT 24 |
Jul 30 07:23:20 PM PDT 24 |
730296075 ps |
| T130 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.187052519 |
|
|
Jul 30 07:23:34 PM PDT 24 |
Jul 30 07:23:36 PM PDT 24 |
234531737 ps |
| T87 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2158947016 |
|
|
Jul 30 07:23:14 PM PDT 24 |
Jul 30 07:23:42 PM PDT 24 |
14783381165 ps |
| T88 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1045757317 |
|
|
Jul 30 07:23:36 PM PDT 24 |
Jul 30 07:25:05 PM PDT 24 |
117499025028 ps |
| T948 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.1998690258 |
|
|
Jul 30 07:23:46 PM PDT 24 |
Jul 30 07:23:50 PM PDT 24 |
361690638 ps |
| T131 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2780915346 |
|
|
Jul 30 07:23:35 PM PDT 24 |
Jul 30 07:23:38 PM PDT 24 |
353477203 ps |
| T949 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.2428113202 |
|
|
Jul 30 07:23:37 PM PDT 24 |
Jul 30 07:23:38 PM PDT 24 |
16125158 ps |
| T950 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.4247400286 |
|
|
Jul 30 07:23:35 PM PDT 24 |
Jul 30 07:23:35 PM PDT 24 |
12328806 ps |
| T951 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.81420077 |
|
|
Jul 30 07:23:18 PM PDT 24 |
Jul 30 07:23:21 PM PDT 24 |
1419808082 ps |
| T92 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1314652381 |
|
|
Jul 30 07:23:40 PM PDT 24 |
Jul 30 07:24:05 PM PDT 24 |
15464136950 ps |
| T952 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3906045442 |
|
|
Jul 30 07:23:33 PM PDT 24 |
Jul 30 07:23:37 PM PDT 24 |
42273777 ps |
| T93 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2037712155 |
|
|
Jul 30 07:23:26 PM PDT 24 |
Jul 30 07:24:41 PM PDT 24 |
87960234291 ps |
| T953 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.2586952492 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:46 PM PDT 24 |
376712432 ps |
| T954 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.2099222614 |
|
|
Jul 30 07:23:43 PM PDT 24 |
Jul 30 07:23:44 PM PDT 24 |
47933176 ps |
| T94 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3751279947 |
|
|
Jul 30 07:23:31 PM PDT 24 |
Jul 30 07:23:56 PM PDT 24 |
7391973987 ps |
| T955 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.1675826931 |
|
|
Jul 30 07:23:13 PM PDT 24 |
Jul 30 07:23:15 PM PDT 24 |
25422005 ps |
| T956 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.4271933515 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
41304216 ps |
| T957 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.3585955023 |
|
|
Jul 30 07:23:27 PM PDT 24 |
Jul 30 07:23:31 PM PDT 24 |
354642935 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.1919973742 |
|
|
Jul 30 07:23:10 PM PDT 24 |
Jul 30 07:23:11 PM PDT 24 |
34831788 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1124532669 |
|
|
Jul 30 07:23:18 PM PDT 24 |
Jul 30 07:23:19 PM PDT 24 |
79566546 ps |
| T960 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.480719463 |
|
|
Jul 30 07:23:47 PM PDT 24 |
Jul 30 07:24:15 PM PDT 24 |
15460214264 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1988833283 |
|
|
Jul 30 07:23:46 PM PDT 24 |
Jul 30 07:23:46 PM PDT 24 |
67669254 ps |
| T961 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.332834656 |
|
|
Jul 30 07:23:47 PM PDT 24 |
Jul 30 07:23:49 PM PDT 24 |
28191742 ps |
| T962 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.2406520917 |
|
|
Jul 30 07:23:40 PM PDT 24 |
Jul 30 07:23:41 PM PDT 24 |
51652778 ps |
| T100 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.2536228035 |
|
|
Jul 30 07:23:43 PM PDT 24 |
Jul 30 07:24:34 PM PDT 24 |
19795738414 ps |
| T963 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.3694592133 |
|
|
Jul 30 07:23:52 PM PDT 24 |
Jul 30 07:23:52 PM PDT 24 |
14297411 ps |
| T964 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.233135227 |
|
|
Jul 30 07:23:48 PM PDT 24 |
Jul 30 07:23:49 PM PDT 24 |
17477296 ps |
| T98 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.220291859 |
|
|
Jul 30 07:23:20 PM PDT 24 |
Jul 30 07:23:21 PM PDT 24 |
60202390 ps |
| T129 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.821977368 |
|
|
Jul 30 07:23:22 PM PDT 24 |
Jul 30 07:23:25 PM PDT 24 |
780843419 ps |
| T965 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2241630850 |
|
|
Jul 30 07:23:30 PM PDT 24 |
Jul 30 07:23:34 PM PDT 24 |
1500816260 ps |
| T966 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2532671293 |
|
|
Jul 30 07:23:50 PM PDT 24 |
Jul 30 07:23:50 PM PDT 24 |
38886812 ps |
| T967 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2148286347 |
|
|
Jul 30 07:23:51 PM PDT 24 |
Jul 30 07:23:53 PM PDT 24 |
370958686 ps |
| T968 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.722139646 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
14274119 ps |
| T101 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2006825449 |
|
|
Jul 30 07:23:36 PM PDT 24 |
Jul 30 07:24:31 PM PDT 24 |
19626884414 ps |
| T969 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.3078055800 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:45 PM PDT 24 |
360269183 ps |
| T102 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.2995517786 |
|
|
Jul 30 07:23:36 PM PDT 24 |
Jul 30 07:24:26 PM PDT 24 |
7579455556 ps |
| T970 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2284930153 |
|
|
Jul 30 07:23:35 PM PDT 24 |
Jul 30 07:23:59 PM PDT 24 |
14791019187 ps |
| T971 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1981880551 |
|
|
Jul 30 07:23:36 PM PDT 24 |
Jul 30 07:23:37 PM PDT 24 |
36649408 ps |
| T972 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1738410318 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:46 PM PDT 24 |
513958190 ps |
| T973 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.949370418 |
|
|
Jul 30 07:23:17 PM PDT 24 |
Jul 30 07:23:19 PM PDT 24 |
27084165 ps |
| T974 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.1279179604 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:42 PM PDT 24 |
24087624 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.1260367920 |
|
|
Jul 30 07:23:22 PM PDT 24 |
Jul 30 07:23:23 PM PDT 24 |
17446077 ps |
| T976 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.46098989 |
|
|
Jul 30 07:23:35 PM PDT 24 |
Jul 30 07:23:39 PM PDT 24 |
507783034 ps |
| T135 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3755701692 |
|
|
Jul 30 07:23:43 PM PDT 24 |
Jul 30 07:23:46 PM PDT 24 |
279543878 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1727669727 |
|
|
Jul 30 07:23:30 PM PDT 24 |
Jul 30 07:23:35 PM PDT 24 |
141206565 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.995856315 |
|
|
Jul 30 07:23:26 PM PDT 24 |
Jul 30 07:23:30 PM PDT 24 |
2040266779 ps |
| T979 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.2950791611 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:42 PM PDT 24 |
32020972 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1149319925 |
|
|
Jul 30 07:23:29 PM PDT 24 |
Jul 30 07:23:31 PM PDT 24 |
115113501 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3908623140 |
|
|
Jul 30 07:23:17 PM PDT 24 |
Jul 30 07:23:22 PM PDT 24 |
598058412 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2243369193 |
|
|
Jul 30 07:23:30 PM PDT 24 |
Jul 30 07:23:32 PM PDT 24 |
516833566 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3865168439 |
|
|
Jul 30 07:23:24 PM PDT 24 |
Jul 30 07:23:25 PM PDT 24 |
56050017 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3916778358 |
|
|
Jul 30 07:23:37 PM PDT 24 |
Jul 30 07:24:08 PM PDT 24 |
15353892601 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1798520587 |
|
|
Jul 30 07:23:27 PM PDT 24 |
Jul 30 07:23:28 PM PDT 24 |
52487684 ps |
| T136 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.73988529 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
251738864 ps |
| T984 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2754663380 |
|
|
Jul 30 07:23:26 PM PDT 24 |
Jul 30 07:23:27 PM PDT 24 |
20446279 ps |
| T985 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2031543997 |
|
|
Jul 30 07:23:41 PM PDT 24 |
Jul 30 07:23:44 PM PDT 24 |
52909447 ps |
| T986 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.3724519034 |
|
|
Jul 30 07:23:38 PM PDT 24 |
Jul 30 07:23:43 PM PDT 24 |
682249470 ps |
| T987 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2744739150 |
|
|
Jul 30 07:23:29 PM PDT 24 |
Jul 30 07:23:30 PM PDT 24 |
13610833 ps |
| T988 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1528908154 |
|
|
Jul 30 07:23:17 PM PDT 24 |
Jul 30 07:23:17 PM PDT 24 |
22286030 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2438300726 |
|
|
Jul 30 07:23:46 PM PDT 24 |
Jul 30 07:24:40 PM PDT 24 |
7365177326 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.493735162 |
|
|
Jul 30 07:23:27 PM PDT 24 |
Jul 30 07:23:29 PM PDT 24 |
2821686504 ps |
| T991 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3867173429 |
|
|
Jul 30 07:23:21 PM PDT 24 |
Jul 30 07:23:22 PM PDT 24 |
14439767 ps |
| T992 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2067104354 |
|
|
Jul 30 07:23:19 PM PDT 24 |
Jul 30 07:23:23 PM PDT 24 |
394521956 ps |
| T993 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3271801158 |
|
|
Jul 30 07:23:19 PM PDT 24 |
Jul 30 07:23:21 PM PDT 24 |
508881400 ps |
| T994 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3592093682 |
|
|
Jul 30 07:23:34 PM PDT 24 |
Jul 30 07:23:35 PM PDT 24 |
123130463 ps |
| T995 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2497924123 |
|
|
Jul 30 07:23:19 PM PDT 24 |
Jul 30 07:23:21 PM PDT 24 |
51956202 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.1613857189 |
|
|
Jul 30 07:23:38 PM PDT 24 |
Jul 30 07:23:39 PM PDT 24 |
176486336 ps |
| T997 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.113673811 |
|
|
Jul 30 07:23:42 PM PDT 24 |
Jul 30 07:23:46 PM PDT 24 |
196446560 ps |
| T133 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.1498510958 |
|
|
Jul 30 07:23:12 PM PDT 24 |
Jul 30 07:23:15 PM PDT 24 |
278946044 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2668465294 |
|
|
Jul 30 07:23:37 PM PDT 24 |
Jul 30 07:23:39 PM PDT 24 |
81846296 ps |
| T999 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2712121507 |
|
|
Jul 30 07:23:20 PM PDT 24 |
Jul 30 07:23:23 PM PDT 24 |
1037891971 ps |
| T1000 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3558431769 |
|
|
Jul 30 07:23:21 PM PDT 24 |
Jul 30 07:23:23 PM PDT 24 |
126366430 ps |
| T1001 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3440487955 |
|
|
Jul 30 07:23:32 PM PDT 24 |
Jul 30 07:23:33 PM PDT 24 |
13676188 ps |
| T1002 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.222192699 |
|
|
Jul 30 07:23:44 PM PDT 24 |
Jul 30 07:23:48 PM PDT 24 |
137786907 ps |
| T1003 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.2437506098 |
|
|
Jul 30 07:23:40 PM PDT 24 |
Jul 30 07:23:44 PM PDT 24 |
360181321 ps |