Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16212265	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162681868

1

T2

139502

T3

3159

T4

179506

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	88096871	1			T2	76727		T3	31812		T4	98606
values[0x0]	43791130	1			T2	36949		T3	10263		T4	47403
values[0x1]	47006132	1			T2	39818		T3	21899		T4	51196

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8246958	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

170647175

1

T2

146488

T3

28981

T4

188471

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	579988	1			T2	598		T3	248		T4	822
valid_sources[0x01]	560261	1			T2	544		T3	247		T4	800
valid_sources[0x02]	635994	1			T2	733		T3	280		T4	785
valid_sources[0x03]	580020	1			T2	643		T3	244		T4	759
valid_sources[0x04]	561545	1			T2	619		T3	254		T4	720
valid_sources[0x05]	568049	1			T2	685		T3	238		T4	839
valid_sources[0x06]	561292	1			T2	581		T3	271		T4	743
valid_sources[0x07]	549368	1			T2	535		T3	262		T4	844
valid_sources[0x08]	620771	1			T2	569		T3	263		T4	777
valid_sources[0x09]	590015	1			T2	557		T3	206		T4	741
valid_sources[0x0a]	1819613	1			T2	656		T3	245		T4	742
valid_sources[0x0b]	586432	1			T2	593		T3	240		T4	685
valid_sources[0x0c]	581758	1			T2	592		T3	282		T4	782
valid_sources[0x0d]	553542	1			T2	574		T3	252		T4	794
valid_sources[0x0e]	626751	1			T2	585		T3	257		T4	810
valid_sources[0x0f]	557886	1			T2	559		T3	272		T4	713
valid_sources[0x10]	615949	1			T2	609		T3	267		T4	755
valid_sources[0x11]	677730	1			T2	592		T3	252		T4	721
valid_sources[0x12]	1927916	1			T2	581		T3	245		T4	774
valid_sources[0x13]	654789	1			T2	577		T3	223		T4	804
valid_sources[0x14]	615901	1			T2	619		T3	251		T4	811
valid_sources[0x15]	568942	1			T2	570		T3	295		T4	742
valid_sources[0x16]	554846	1			T2	553		T3	250		T4	832
valid_sources[0x17]	579350	1			T2	616		T3	243		T4	823
valid_sources[0x18]	563847	1			T2	567		T3	238		T4	640
valid_sources[0x19]	555131	1			T2	650		T3	260		T4	776
valid_sources[0x1a]	569359	1			T2	632		T3	255		T4	765
valid_sources[0x1b]	1547168	1			T2	547		T3	243		T4	802
valid_sources[0x1c]	591581	1			T2	639		T3	292		T4	794
valid_sources[0x1d]	635356	1			T2	591		T3	274		T4	748
valid_sources[0x1e]	567098	1			T2	552		T3	258		T4	781
valid_sources[0x1f]	563333	1			T2	553		T3	255		T4	790
valid_sources[0x20]	579827	1			T2	661		T3	257		T4	771
valid_sources[0x21]	547895	1			T2	541		T3	258		T4	696
valid_sources[0x22]	569598	1			T2	634		T3	231		T4	826
valid_sources[0x23]	622660	1			T2	555		T3	225		T4	817
valid_sources[0x24]	555714	1			T2	553		T3	284		T4	737
valid_sources[0x25]	1943268	1			T2	586		T3	259		T4	726
valid_sources[0x26]	642216	1			T2	622		T3	225		T4	749
valid_sources[0x27]	561048	1			T2	567		T3	249		T4	723
valid_sources[0x28]	2945553	1			T2	604		T3	272		T4	772
valid_sources[0x29]	589612	1			T2	590		T3	242		T4	766
valid_sources[0x2a]	572419	1			T2	626		T3	247		T4	756
valid_sources[0x2b]	721188	1			T2	607		T3	235		T4	802
valid_sources[0x2c]	579621	1			T2	581		T3	231		T4	761
valid_sources[0x2d]	580384	1			T2	528		T3	264		T4	778
valid_sources[0x2e]	553748	1			T2	535		T3	263		T4	650
valid_sources[0x2f]	2181864	1			T2	516		T3	261		T4	775
valid_sources[0x30]	566598	1			T2	608		T3	223		T4	811
valid_sources[0x31]	576064	1			T2	556		T3	261		T4	729
valid_sources[0x32]	579018	1			T2	559		T3	244		T4	833
valid_sources[0x33]	588027	1			T2	567		T3	258		T4	774
valid_sources[0x34]	560574	1			T2	607		T3	249		T4	754
valid_sources[0x35]	754614	1			T2	573		T3	227		T4	698
valid_sources[0x36]	599295	1			T2	536		T3	245		T4	731
valid_sources[0x37]	593795	1			T2	576		T3	249		T4	747
valid_sources[0x38]	553589	1			T2	586		T3	256		T4	757
valid_sources[0x39]	602167	1			T2	532		T3	238		T4	801
valid_sources[0x3a]	637266	1			T2	564		T3	244		T4	761
valid_sources[0x3b]	547023	1			T2	613		T3	228		T4	747
valid_sources[0x3c]	565892	1			T2	541		T3	264		T4	800
valid_sources[0x3d]	609434	1			T2	548		T3	250		T4	839
valid_sources[0x3e]	588973	1			T2	602		T3	275		T4	760
valid_sources[0x3f]	580765	1			T2	545		T3	226		T4	722
valid_sources[0x40]	670233	1			T2	624		T3	264		T4	683
valid_sources[0x41]	605127	1			T2	645		T3	257		T4	770
valid_sources[0x42]	572454	1			T2	630		T3	263		T4	781
valid_sources[0x43]	618075	1			T2	589		T3	282		T4	771
valid_sources[0x44]	569190	1			T2	611		T3	237		T4	772
valid_sources[0x45]	590483	1			T2	548		T3	234		T4	808
valid_sources[0x46]	594604	1			T2	596		T3	244		T4	762
valid_sources[0x47]	587374	1			T2	594		T3	250		T4	737
valid_sources[0x48]	626769	1			T2	550		T3	269		T4	720
valid_sources[0x49]	651460	1			T2	711		T3	261		T4	818
valid_sources[0x4a]	556513	1			T2	631		T3	249		T4	698
valid_sources[0x4b]	576070	1			T2	677		T3	268		T4	786
valid_sources[0x4c]	584473	1			T2	725		T3	249		T4	785
valid_sources[0x4d]	598212	1			T2	617		T3	267		T4	670
valid_sources[0x4e]	570096	1			T2	593		T3	265		T4	783
valid_sources[0x4f]	1147503	1			T2	619		T3	226		T4	807
valid_sources[0x50]	2109859	1			T2	669		T3	235		T4	799
valid_sources[0x51]	577406	1			T2	641		T3	262		T4	753
valid_sources[0x52]	567072	1			T2	632		T3	249		T4	726
valid_sources[0x53]	583150	1			T2	654		T3	237		T4	791
valid_sources[0x54]	549880	1			T2	602		T3	248		T4	857
valid_sources[0x55]	577659	1			T2	611		T3	245		T4	793
valid_sources[0x56]	561489	1			T2	630		T3	223		T4	864
valid_sources[0x57]	625236	1			T2	709		T3	203		T4	768
valid_sources[0x58]	569232	1			T2	627		T3	225		T4	799
valid_sources[0x59]	993662	1			T2	602		T3	285		T4	776
valid_sources[0x5a]	648009	1			T2	551		T3	238		T4	813
valid_sources[0x5b]	561908	1			T2	577		T3	282		T4	753
valid_sources[0x5c]	674963	1			T2	562		T3	255		T4	775
valid_sources[0x5d]	567608	1			T2	589		T3	226		T4	753
valid_sources[0x5e]	672972	1			T2	575		T3	270		T4	656
valid_sources[0x5f]	550740	1			T2	625		T3	262		T4	732
valid_sources[0x60]	575884	1			T2	671		T3	273		T4	780
valid_sources[0x61]	565412	1			T2	599		T3	232		T4	878
valid_sources[0x62]	560859	1			T2	605		T3	227		T4	683
valid_sources[0x63]	561807	1			T2	571		T3	257		T4	799
valid_sources[0x64]	562864	1			T2	615		T3	258		T4	774
valid_sources[0x65]	574870	1			T2	600		T3	244		T4	727
valid_sources[0x66]	569664	1			T2	661		T3	245		T4	686
valid_sources[0x67]	554704	1			T2	598		T3	274		T4	793
valid_sources[0x68]	593062	1			T2	601		T3	250		T4	722
valid_sources[0x69]	566157	1			T2	551		T3	257		T4	740
valid_sources[0x6a]	643507	1			T2	625		T3	242		T4	834
valid_sources[0x6b]	596267	1			T2	621		T3	265		T4	787
valid_sources[0x6c]	552357	1			T2	643		T3	243		T4	752
valid_sources[0x6d]	587953	1			T2	621		T3	256		T4	816
valid_sources[0x6e]	593015	1			T2	563		T3	248		T4	723
valid_sources[0x6f]	557712	1			T2	674		T3	246		T4	738
valid_sources[0x70]	587104	1			T2	529		T3	274		T4	837
valid_sources[0x71]	584638	1			T2	614		T3	237		T4	746
valid_sources[0x72]	587357	1			T2	586		T3	225		T4	774
valid_sources[0x73]	575747	1			T2	654		T3	219		T4	724
valid_sources[0x74]	2227697	1			T2	582		T3	237		T4	739
valid_sources[0x75]	585076	1			T2	619		T3	259		T4	818
valid_sources[0x76]	576733	1			T2	676		T3	258		T4	697
valid_sources[0x77]	1068597	1			T2	585		T3	246		T4	741
valid_sources[0x78]	577144	1			T2	579		T3	230		T4	832
valid_sources[0x79]	878818	1			T2	639		T3	250		T4	827
valid_sources[0x7a]	574722	1			T2	627		T3	251		T4	778
valid_sources[0x7b]	559762	1			T2	625		T3	264		T4	758
valid_sources[0x7c]	580249	1			T2	606		T3	217		T4	750
valid_sources[0x7d]	590012	1			T2	684		T3	274		T4	747
valid_sources[0x7e]	600343	1			T2	646		T3	266		T4	755
valid_sources[0x7f]	555299	1			T2	624		T3	209		T4	734
valid_sources[0x80]	584826	1			T2	542		T3	221		T4	755

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79947017

1

T2

69655

T3

271

T4

89912

values[0x0]

all_enables

biggest_size

41372636

1

T2

34834

T3

1464

T4

44747

values[0x1]

all_enables

biggest_size

41362215

1

T2

35013

T3

1424

T4

44847

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	45017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155466

1

T1

1

T2

3

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55339	1			T5	45		T6	322		T12	19
values[0x0]	70001	1			T1	1		T2	6		T3	2
values[0x1]	75143	1			T2	7		T3	1		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34699	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165784

1

T1

1

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	707	1			T25	12		T26	6		T65	15
valid_sources[0x01]	661	1			T43	1		T49	4		T25	11
valid_sources[0x02]	749	1			T5	2		T42	1		T174	1
valid_sources[0x03]	723	1			T5	2		T42	2		T25	8
valid_sources[0x04]	775	1			T25	2		T26	4		T65	9
valid_sources[0x05]	778	1			T42	1		T43	2		T25	7
valid_sources[0x06]	1086	1			T9	3		T22	1		T49	15
valid_sources[0x07]	746	1			T5	1		T25	13		T26	8
valid_sources[0x08]	684	1			T25	12		T26	8		T65	5
valid_sources[0x09]	763	1			T25	6		T26	26		T75	1
valid_sources[0x0a]	741	1			T25	7		T27	1		T26	7
valid_sources[0x0b]	677	1			T4	2		T12	13		T42	2
valid_sources[0x0c]	746	1			T43	1		T49	2		T25	11
valid_sources[0x0d]	654	1			T25	9		T26	8		T65	7
valid_sources[0x0e]	915	1			T5	5		T25	10		T26	15
valid_sources[0x0f]	940	1			T5	1		T25	8		T26	1
valid_sources[0x10]	952	1			T9	7		T5	1		T25	5
valid_sources[0x11]	913	1			T5	2		T42	1		T25	9
valid_sources[0x12]	969	1			T49	1		T25	13		T26	5
valid_sources[0x13]	685	1			T25	8		T26	14		T65	16
valid_sources[0x14]	898	1			T5	1		T42	4		T25	10
valid_sources[0x15]	705	1			T42	1		T25	11		T163	1
valid_sources[0x16]	747	1			T5	1		T25	11		T175	1
valid_sources[0x17]	945	1			T5	4		T25	6		T65	12
valid_sources[0x18]	1295	1			T12	25		T42	1		T129	1
valid_sources[0x19]	731	1			T5	1		T42	1		T22	1
valid_sources[0x1a]	1103	1			T5	1		T42	1		T25	13
valid_sources[0x1b]	583	1			T42	1		T25	10		T26	8
valid_sources[0x1c]	1058	1			T6	110		T68	1		T25	8
valid_sources[0x1d]	827	1			T42	1		T49	1		T48	1
valid_sources[0x1e]	681	1			T5	1		T68	1		T25	7
valid_sources[0x1f]	600	1			T22	1		T25	15		T26	1
valid_sources[0x20]	681	1			T10	1		T49	4		T129	4
valid_sources[0x21]	807	1			T6	1		T25	3		T26	8
valid_sources[0x22]	951	1			T42	2		T49	5		T25	9
valid_sources[0x23]	672	1			T49	9		T25	7		T65	15
valid_sources[0x24]	835	1			T22	2		T25	6		T26	9
valid_sources[0x25]	676	1			T49	1		T25	12		T26	2
valid_sources[0x26]	932	1			T5	2		T25	5		T65	3
valid_sources[0x27]	614	1			T5	1		T25	8		T26	9
valid_sources[0x28]	760	1			T5	1		T42	1		T49	1
valid_sources[0x29]	999	1			T6	274		T12	10		T25	9
valid_sources[0x2a]	705	1			T5	2		T42	1		T67	1
valid_sources[0x2b]	842	1			T5	1		T49	1		T25	11
valid_sources[0x2c]	705	1			T5	1		T68	1		T25	9
valid_sources[0x2d]	1061	1			T25	7		T65	12		T52	37
valid_sources[0x2e]	1124	1			T9	5		T42	1		T25	6
valid_sources[0x2f]	654	1			T9	1		T5	1		T42	2
valid_sources[0x30]	697	1			T5	1		T25	4		T26	5
valid_sources[0x31]	596	1			T9	2		T43	1		T25	11
valid_sources[0x32]	729	1			T5	1		T25	11		T26	1
valid_sources[0x33]	956	1			T42	1		T68	1		T25	7
valid_sources[0x34]	713	1			T25	11		T26	4		T65	10
valid_sources[0x35]	704	1			T5	1		T22	1		T68	1
valid_sources[0x36]	906	1			T9	1		T25	3		T26	2
valid_sources[0x37]	728	1			T25	4		T65	13		T92	43
valid_sources[0x38]	763	1			T5	1		T25	11		T44	1
valid_sources[0x39]	814	1			T49	2		T25	7		T26	5
valid_sources[0x3a]	988	1			T12	8		T25	11		T65	15
valid_sources[0x3b]	751	1			T9	3		T176	2		T25	12
valid_sources[0x3c]	623	1			T5	1		T42	3		T25	12
valid_sources[0x3d]	716	1			T25	13		T26	4		T65	13
valid_sources[0x3e]	887	1			T5	1		T25	3		T65	6
valid_sources[0x3f]	863	1			T22	2		T25	10		T26	1
valid_sources[0x40]	1103	1			T10	5		T7	117		T42	1
valid_sources[0x41]	774	1			T25	10		T26	5		T65	3
valid_sources[0x42]	1042	1			T42	2		T25	7		T26	1
valid_sources[0x43]	627	1			T40	2		T49	1		T177	1
valid_sources[0x44]	821	1			T5	2		T25	6		T87	42
valid_sources[0x45]	938	1			T9	1		T5	2		T22	1
valid_sources[0x46]	987	1			T5	1		T25	4		T26	10
valid_sources[0x47]	649	1			T5	2		T42	4		T25	6
valid_sources[0x48]	782	1			T5	2		T174	1		T25	12
valid_sources[0x49]	643	1			T5	1		T42	1		T22	2
valid_sources[0x4a]	1029	1			T3	1		T5	1		T42	3
valid_sources[0x4b]	1100	1			T25	11		T26	1		T65	8
valid_sources[0x4c]	805	1			T42	1		T25	7		T26	14
valid_sources[0x4d]	902	1			T24	7		T25	1		T65	16
valid_sources[0x4e]	713	1			T5	2		T49	2		T25	3
valid_sources[0x4f]	841	1			T25	8		T65	4		T139	1
valid_sources[0x50]	671	1			T3	1		T42	1		T66	1
valid_sources[0x51]	841	1			T25	8		T65	7		T52	15
valid_sources[0x52]	718	1			T22	2		T47	1		T41	5
valid_sources[0x53]	646	1			T25	3		T65	8		T178	1
valid_sources[0x54]	714	1			T5	1		T42	1		T43	1
valid_sources[0x55]	948	1			T9	2		T25	4		T26	11
valid_sources[0x56]	817	1			T5	2		T25	7		T26	5
valid_sources[0x57]	720	1			T5	1		T86	78		T25	6
valid_sources[0x58]	927	1			T5	1		T22	1		T25	11
valid_sources[0x59]	964	1			T9	1		T42	1		T22	1
valid_sources[0x5a]	870	1			T5	1		T66	2		T25	10
valid_sources[0x5b]	1027	1			T9	2		T5	2		T25	3
valid_sources[0x5c]	786	1			T5	1		T25	6		T26	1
valid_sources[0x5d]	642	1			T42	1		T22	3		T49	7
valid_sources[0x5e]	728	1			T9	2		T5	1		T42	1
valid_sources[0x5f]	960	1			T5	1		T66	1		T25	4
valid_sources[0x60]	666	1			T66	4		T25	10		T26	15
valid_sources[0x61]	899	1			T5	1		T22	1		T25	4
valid_sources[0x62]	748	1			T25	7		T26	5		T14	2
valid_sources[0x63]	736	1			T5	1		T42	1		T25	4
valid_sources[0x64]	703	1			T22	2		T25	10		T65	8
valid_sources[0x65]	589	1			T9	1		T42	1		T25	5
valid_sources[0x66]	696	1			T5	3		T25	7		T26	2
valid_sources[0x67]	944	1			T5	1		T42	1		T22	1
valid_sources[0x68]	1091	1			T5	1		T49	1		T25	7
valid_sources[0x69]	714	1			T9	1		T5	1		T22	1
valid_sources[0x6a]	1160	1			T10	5		T25	8		T26	3
valid_sources[0x6b]	777	1			T67	1		T25	8		T26	1
valid_sources[0x6c]	755	1			T9	1		T6	1		T25	3
valid_sources[0x6d]	713	1			T5	1		T42	1		T25	9
valid_sources[0x6e]	585	1			T6	39		T49	3		T25	10
valid_sources[0x6f]	652	1			T5	1		T42	1		T25	9
valid_sources[0x70]	716	1			T42	1		T25	7		T26	4
valid_sources[0x71]	554	1			T42	1		T25	7		T26	8
valid_sources[0x72]	681	1			T9	4		T25	4		T26	6
valid_sources[0x73]	694	1			T5	1		T42	1		T67	2
valid_sources[0x74]	794	1			T42	1		T25	6		T26	14
valid_sources[0x75]	642	1			T5	2		T49	1		T25	11
valid_sources[0x76]	687	1			T179	5		T25	9		T26	4
valid_sources[0x77]	582	1			T5	1		T42	1		T22	1
valid_sources[0x78]	963	1			T5	1		T47	1		T49	1
valid_sources[0x79]	750	1			T5	1		T25	6		T26	8
valid_sources[0x7a]	825	1			T22	1		T25	9		T77	1
valid_sources[0x7b]	522	1			T4	1		T5	2		T43	1
valid_sources[0x7c]	804	1			T22	1		T25	6		T21	23
valid_sources[0x7d]	905	1			T9	2		T5	1		T43	1
valid_sources[0x7e]	611	1			T5	1		T42	1		T68	1
valid_sources[0x7f]	788	1			T49	2		T25	10		T175	1
valid_sources[0x80]	604	1			T25	9		T26	2		T163	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41877

1

T5

27

T6

294

T12

11

values[0x0]

all_enables

biggest_size

58268

1

T1

1

T2

1

T3

1

values[0x1]

all_enables

biggest_size

55321

1

T2

2

T9

8

T10

1