Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16117449

1

T2

13992

T3

60815

T4

17699

full_word

159604243

1

T2

139502

T3

3159

T4

179506

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	175721362	1			T2	153494		T3	63974		T4	197205
auto[TlIntgErrCmd]	92	1			T80	8		T81	3		T82	4
auto[TlIntgErrData]	116	1			T80	2		T81	13		T82	3
auto[TlIntgErrBoth]	122	1			T80	10		T81	4		T82	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84836670

1

T2

76727

T3

31812

T4

98606

auto[1]

90885022

1

T2

76767

T3

32162

T4

98599

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7892456	1			T2	7072		T3	31541		T4	8694
auto[TlIntgErrNone]	partial	auto[1]	8224691	1			T2	6920		T3	29274		T4	9005
auto[TlIntgErrNone]	full_word	auto[0]	76944061	1			T2	69655		T3	271		T4	89912
auto[TlIntgErrNone]	full_word	auto[1]	82660154	1			T2	69847		T3	2888		T4	89594
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T80	3		T81	1		T82	3
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T80	5		T81	2		T82	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T154	1		T155	2		T157	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T156	1		T158	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T81	3		T82	2		T154	4
auto[TlIntgErrData]	partial	auto[1]	58	1			T80	2		T81	9		T82	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T155	1		T151	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T81	1		T151	1		T147	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T80	3		T81	2		T82	1
auto[TlIntgErrBoth]	partial	auto[1]	61	1			T80	6		T81	2		T82	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T149	1		T147	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T80	1		T154	1		T152	1