Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	899027	1			T2	4884		T5	2466		T40	88
auto[1]	11112595	1			T2	3388		T3	30275		T4	82867
auto[2]	682988	1			T2	3190		T5	1025		T40	52
auto[3]	10823139	1			T2	1612		T3	30601		T4	82926

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14851506	1			T2	9954		T3	286		T4	136911
auto[1]	2208569	1			T2	1294		T3	2857		T4	13974
auto[2]	2235204	1			T2	1650		T3	5452		T4	13588
auto[3]	4222470	1			T2	176		T3	52281		T4	1320

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10035206

1

T2

13074

T3

60873

T5

5067

auto[1]

13482543

1

T3

3

T4

165793

T7

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	366605	1			T2	3991		T5	2029		T40	68
auto[0]	auto[0]	auto[1]	37868	1			T2	422		T5	212		T40	9
auto[0]	auto[0]	auto[2]	38064	1			T2	427		T5	206		T40	10
auto[0]	auto[0]	auto[3]	72343	1			T2	44		T5	19		T40	1
auto[0]	auto[1]	auto[0]	3576665	1			T2	2578		T3	31		T5	906
auto[0]	auto[1]	auto[1]	373198	1			T2	480		T3	224		T5	164
auto[0]	auto[1]	auto[2]	382027	1			T2	280		T3	2955		T5	83
auto[0]	auto[1]	auto[3]	339531	1			T2	50		T3	27065		T5	15
auto[0]	auto[2]	auto[0]	267293	1			T2	2417		T5	817		T41	9741
auto[0]	auto[2]	auto[1]	31919	1			T2	276		T5	80		T41	967
auto[0]	auto[2]	auto[2]	30055	1			T2	457		T5	116		T40	46
auto[0]	auto[2]	auto[3]	52591	1			T2	40		T5	12		T40	6
auto[0]	auto[3]	auto[0]	3418013	1			T2	968		T3	255		T5	255
auto[0]	auto[3]	auto[1]	362936	1			T2	116		T3	2633		T5	26
auto[0]	auto[3]	auto[2]	379881	1			T2	486		T3	2496		T5	117
auto[0]	auto[3]	auto[3]	306217	1			T2	42		T3	25214		T5	10
auto[1]	auto[0]	auto[0]	12891	1			T143	1		T144	763		T170	160
auto[1]	auto[0]	auto[1]	56922	1			T144	3324		T170	671		T171	2077
auto[1]	auto[0]	auto[2]	56909	1			T144	3349		T170	727		T171	2037
auto[1]	auto[0]	auto[3]	257425	1			T144	15134		T170	3284		T112	2
auto[1]	auto[1]	auto[0]	3603941	1			T4	68510		T7	2		T24	80279
auto[1]	auto[1]	auto[1]	670700	1			T4	7053		T24	7435		T69	15857
auto[1]	auto[1]	auto[2]	645955	1			T4	6664		T24	7983		T66	1
auto[1]	auto[1]	auto[3]	1520578	1			T4	640		T24	739		T69	70964
auto[1]	auto[2]	auto[0]	9557	1			T144	700		T171	286		T172	523
auto[1]	auto[2]	auto[1]	42989	1			T144	3190		T171	1237		T172	2273
auto[1]	auto[2]	auto[2]	45151	1			T144	2977		T170	609		T171	2281
auto[1]	auto[2]	auto[3]	203433	1			T144	12799		T170	2831		T171	10118
auto[1]	auto[3]	auto[0]	3596541	1			T4	68401		T7	2		T24	80926
auto[1]	auto[3]	auto[1]	632037	1			T4	6921		T24	8046		T69	15658
auto[1]	auto[3]	auto[2]	657162	1			T3	1		T4	6924		T24	7229
auto[1]	auto[3]	auto[3]	1470352	1			T3	2		T4	680		T24	729