Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1149794331	226747	0	0
ctrl_regwen_rd_A	1149794331	4316	0	0
exec_rd_A	1149794331	3802	0	0
exec_regwen_rd_A	1149794331	4173	0	0
readback_rd_A	1149794331	2673	0	0
readback_regwen_rd_A	1149794331	2128	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	226747	0	0
T6	27082	1509	0	0
T7	397765	0	0	0
T11	78227	0	0	0
T12	353511	0	0	0
T22	263875	0	0	0
T24	502731	0	0	0
T25	0	3004	0	0
T26	0	1320	0	0
T40	291076	0	0	0
T42	525036	0	0	0
T43	187136	0	0	0
T52	0	9953	0	0
T63	0	5487	0	0
T65	0	4000	0	0
T66	542893	0	0	0
T88	0	2472	0	0
T89	0	5512	0	0
T90	0	6888	0	0
T91	0	3092	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	4316	0	0
T54	0	228	0	0
T63	0	401	0	0
T65	151664	294	0	0
T79	951659	0	0	0
T92	713123	0	0	0
T131	0	19	0	0
T132	0	60	0	0
T133	0	303	0	0
T134	0	274	0	0
T135	0	91	0	0
T136	0	475	0	0
T137	0	234	0	0
T138	77490	0	0	0
T139	800510	0	0	0
T140	678313	0	0	0
T141	481172	0	0	0
T142	76363	0	0	0
T143	243466	0	0	0
T144	157184	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	3802	0	0
T54	0	175	0	0
T63	0	438	0	0
T65	151664	231	0	0
T79	951659	0	0	0
T92	713123	0	0	0
T131	0	24	0	0
T132	0	66	0	0
T133	0	288	0	0
T134	0	230	0	0
T135	0	76	0	0
T136	0	356	0	0
T137	0	259	0	0
T138	77490	0	0	0
T139	800510	0	0	0
T140	678313	0	0	0
T141	481172	0	0	0
T142	76363	0	0	0
T143	243466	0	0	0
T144	157184	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	4173	0	0
T54	0	186	0	0
T63	0	380	0	0
T65	151664	303	0	0
T79	951659	0	0	0
T92	713123	0	0	0
T131	0	58	0	0
T132	0	61	0	0
T133	0	372	0	0
T134	0	265	0	0
T135	0	120	0	0
T136	0	397	0	0
T137	0	203	0	0
T138	77490	0	0	0
T139	800510	0	0	0
T140	678313	0	0	0
T141	481172	0	0	0
T142	76363	0	0	0
T143	243466	0	0	0
T144	157184	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	2673	0	0
T54	0	131	0	0
T63	0	404	0	0
T65	151664	238	0	0
T79	951659	0	0	0
T92	713123	0	0	0
T131	0	43	0	0
T132	0	38	0	0
T133	0	297	0	0
T134	0	223	0	0
T135	0	53	0	0
T136	0	420	0	0
T137	0	238	0	0
T138	77490	0	0	0
T139	800510	0	0	0
T140	678313	0	0	0
T141	481172	0	0	0
T142	76363	0	0	0
T143	243466	0	0	0
T144	157184	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1149794331	2128	0	0
T54	0	150	0	0
T63	0	373	0	0
T65	151664	178	0	0
T79	951659	0	0	0
T92	713123	0	0	0
T131	0	23	0	0
T132	0	62	0	0
T133	0	218	0	0
T134	0	234	0	0
T135	0	67	0	0
T136	0	233	0	0
T137	0	178	0	0
T138	77490	0	0	0
T139	800510	0	0	0
T140	678313	0	0	0
T141	481172	0	0	0
T142	76363	0	0	0
T143	243466	0	0	0
T144	157184	0	0	0