Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16138160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152681747

1

T1

120080

T2

10000

T3

3281

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82975005	1			T1	66034		T2	4903		T3	2042
values[0x0]	41321816	1			T1	31744		T2	2553		T3	914
values[0x1]	44523086	1			T1	34311		T2	2544		T3	1054

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8210389	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160609518

1

T1

126085

T2

10000

T3

3653

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	548166	1			T1	507		T2	39		T3	18
valid_sources[0x01]	634970	1			T1	471		T2	45		T3	15
valid_sources[0x02]	559300	1			T1	501		T2	31		T3	19
valid_sources[0x03]	548823	1			T1	530		T2	36		T3	11
valid_sources[0x04]	548680	1			T1	498		T2	45		T3	7
valid_sources[0x05]	611191	1			T1	586		T2	27		T3	25
valid_sources[0x06]	558869	1			T1	508		T2	25		T3	20
valid_sources[0x07]	561260	1			T1	527		T2	29		T3	17
valid_sources[0x08]	551249	1			T1	517		T2	21		T3	14
valid_sources[0x09]	553505	1			T1	502		T2	34		T3	15
valid_sources[0x0a]	1030101	1			T1	538		T2	52		T3	15
valid_sources[0x0b]	600358	1			T1	499		T2	32		T3	15
valid_sources[0x0c]	585182	1			T1	543		T2	39		T3	15
valid_sources[0x0d]	553044	1			T1	475		T2	50		T3	16
valid_sources[0x0e]	543639	1			T1	502		T2	35		T3	8
valid_sources[0x0f]	607874	1			T1	473		T2	61		T3	13
valid_sources[0x10]	591477	1			T1	504		T2	40		T3	20
valid_sources[0x11]	544983	1			T1	534		T2	43		T3	8
valid_sources[0x12]	596438	1			T1	477		T2	35		T3	19
valid_sources[0x13]	1771702	1			T1	528		T2	48		T3	18
valid_sources[0x14]	788828	1			T1	544		T2	40		T3	17
valid_sources[0x15]	582296	1			T1	529		T2	43		T3	16
valid_sources[0x16]	589100	1			T1	528		T2	26		T3	14
valid_sources[0x17]	605686	1			T1	511		T2	34		T3	16
valid_sources[0x18]	551864	1			T1	553		T2	59		T3	13
valid_sources[0x19]	617832	1			T1	537		T2	29		T3	10
valid_sources[0x1a]	588669	1			T1	503		T2	36		T3	22
valid_sources[0x1b]	2025029	1			T1	484		T2	42		T3	10
valid_sources[0x1c]	565642	1			T1	461		T2	59		T3	9
valid_sources[0x1d]	572902	1			T1	542		T2	47		T3	10
valid_sources[0x1e]	600625	1			T1	525		T2	32		T3	14
valid_sources[0x1f]	600474	1			T1	528		T2	33		T3	22
valid_sources[0x20]	541063	1			T1	496		T2	28		T3	18
valid_sources[0x21]	574768	1			T1	622		T2	38		T3	16
valid_sources[0x22]	558674	1			T1	490		T2	46		T3	8
valid_sources[0x23]	543040	1			T1	527		T2	34		T3	10
valid_sources[0x24]	546373	1			T1	522		T2	34		T3	14
valid_sources[0x25]	584808	1			T1	534		T2	36		T3	13
valid_sources[0x26]	550072	1			T1	496		T2	30		T3	18
valid_sources[0x27]	1989867	1			T1	524		T2	37		T3	15
valid_sources[0x28]	567184	1			T1	528		T2	26		T3	20
valid_sources[0x29]	544026	1			T1	547		T2	35		T3	21
valid_sources[0x2a]	595067	1			T1	550		T2	78		T3	6
valid_sources[0x2b]	574615	1			T1	460		T2	31		T3	9
valid_sources[0x2c]	630650	1			T1	477		T2	32		T3	19
valid_sources[0x2d]	577612	1			T1	529		T2	26		T3	11
valid_sources[0x2e]	553869	1			T1	540		T2	34		T3	20
valid_sources[0x2f]	602541	1			T1	469		T2	35		T3	12
valid_sources[0x30]	536709	1			T1	510		T2	47		T3	13
valid_sources[0x31]	626489	1			T1	587		T2	42		T3	12
valid_sources[0x32]	635404	1			T1	487		T2	30		T3	17
valid_sources[0x33]	671635	1			T1	472		T2	61		T3	11
valid_sources[0x34]	561716	1			T1	545		T2	32		T3	10
valid_sources[0x35]	754286	1			T1	567		T2	33		T3	24
valid_sources[0x36]	1930613	1			T1	513		T2	51		T3	23
valid_sources[0x37]	551712	1			T1	487		T2	65		T3	23
valid_sources[0x38]	618430	1			T1	533		T2	59		T3	14
valid_sources[0x39]	592556	1			T1	497		T2	26		T3	8
valid_sources[0x3a]	553525	1			T1	524		T2	37		T3	14
valid_sources[0x3b]	573746	1			T1	519		T2	29		T3	12
valid_sources[0x3c]	675365	1			T1	533		T2	46		T3	9
valid_sources[0x3d]	569937	1			T1	504		T2	32		T3	15
valid_sources[0x3e]	602250	1			T1	502		T2	31		T3	29
valid_sources[0x3f]	547088	1			T1	500		T2	42		T3	16
valid_sources[0x40]	542534	1			T1	471		T2	30		T3	15
valid_sources[0x41]	575124	1			T1	480		T2	40		T3	11
valid_sources[0x42]	563655	1			T1	543		T2	31		T3	20
valid_sources[0x43]	560706	1			T1	469		T2	41		T3	14
valid_sources[0x44]	800243	1			T1	494		T2	31		T3	27
valid_sources[0x45]	1101425	1			T1	513		T2	13		T3	23
valid_sources[0x46]	555921	1			T1	535		T2	47		T3	14
valid_sources[0x47]	672241	1			T1	506		T2	35		T3	22
valid_sources[0x48]	565896	1			T1	549		T2	23		T3	22
valid_sources[0x49]	595685	1			T1	430		T2	70		T3	11
valid_sources[0x4a]	576490	1			T1	506		T2	44		T3	15
valid_sources[0x4b]	538930	1			T1	515		T2	37		T3	13
valid_sources[0x4c]	1087799	1			T1	575		T2	46		T3	16
valid_sources[0x4d]	555006	1			T1	532		T2	36		T3	14
valid_sources[0x4e]	543071	1			T1	453		T2	32		T3	22
valid_sources[0x4f]	561786	1			T1	548		T2	35		T3	12
valid_sources[0x50]	581435	1			T1	538		T2	22		T3	16
valid_sources[0x51]	591162	1			T1	555		T2	42		T3	16
valid_sources[0x52]	578495	1			T1	576		T2	48		T3	18
valid_sources[0x53]	545553	1			T1	562		T2	38		T3	20
valid_sources[0x54]	790618	1			T1	513		T2	28		T3	28
valid_sources[0x55]	588012	1			T1	488		T2	42		T3	10
valid_sources[0x56]	611962	1			T1	534		T2	30		T3	20
valid_sources[0x57]	600594	1			T1	481		T2	56		T3	18
valid_sources[0x58]	541636	1			T1	465		T2	38		T3	15
valid_sources[0x59]	643522	1			T1	599		T2	46		T3	12
valid_sources[0x5a]	575957	1			T1	520		T2	29		T3	18
valid_sources[0x5b]	552315	1			T1	546		T2	41		T3	7
valid_sources[0x5c]	597727	1			T1	549		T2	34		T3	13
valid_sources[0x5d]	543401	1			T1	521		T2	36		T3	13
valid_sources[0x5e]	560389	1			T1	506		T2	48		T3	21
valid_sources[0x5f]	571015	1			T1	489		T2	59		T3	12
valid_sources[0x60]	545301	1			T1	504		T2	41		T3	19
valid_sources[0x61]	541085	1			T1	534		T2	51		T3	14
valid_sources[0x62]	584106	1			T1	537		T2	52		T3	14
valid_sources[0x63]	604780	1			T1	501		T2	34		T3	14
valid_sources[0x64]	574988	1			T1	480		T2	42		T3	13
valid_sources[0x65]	537751	1			T1	548		T2	41		T3	20
valid_sources[0x66]	567210	1			T1	539		T2	37		T3	14
valid_sources[0x67]	567105	1			T1	584		T2	16		T3	17
valid_sources[0x68]	1706071	1			T1	488		T2	44		T3	9
valid_sources[0x69]	543417	1			T1	557		T2	54		T3	19
valid_sources[0x6a]	560434	1			T1	550		T2	36		T3	14
valid_sources[0x6b]	762752	1			T1	471		T2	52		T3	6
valid_sources[0x6c]	552251	1			T1	540		T2	36		T3	15
valid_sources[0x6d]	582364	1			T1	433		T2	35		T3	23
valid_sources[0x6e]	562148	1			T1	504		T2	40		T3	8
valid_sources[0x6f]	553493	1			T1	518		T2	22		T3	16
valid_sources[0x70]	552738	1			T1	510		T2	39		T3	15
valid_sources[0x71]	565424	1			T1	503		T2	33		T3	9
valid_sources[0x72]	1817287	1			T1	463		T2	49		T3	25
valid_sources[0x73]	583747	1			T1	543		T2	31		T3	15
valid_sources[0x74]	542366	1			T1	472		T2	31		T3	21
valid_sources[0x75]	800412	1			T1	508		T2	37		T3	23
valid_sources[0x76]	549997	1			T1	563		T2	36		T3	17
valid_sources[0x77]	561800	1			T1	454		T2	53		T3	15
valid_sources[0x78]	581877	1			T1	562		T2	28		T3	16
valid_sources[0x79]	558655	1			T1	567		T2	35		T3	15
valid_sources[0x7a]	547028	1			T1	494		T2	43		T3	21
valid_sources[0x7b]	551566	1			T1	556		T2	28		T3	11
valid_sources[0x7c]	566025	1			T1	545		T2	27		T3	14
valid_sources[0x7d]	582792	1			T1	478		T2	59		T3	18
valid_sources[0x7e]	550477	1			T1	438		T2	17		T3	12
valid_sources[0x7f]	761620	1			T1	492		T2	34		T3	24
valid_sources[0x80]	1947796	1			T1	465		T2	27		T3	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74863990

1

T1

60025

T2

4903

T3

1650

values[0x0]

all_enables

biggest_size

38911808

1

T1

29914

T2

2553

T3

811

values[0x1]

all_enables

biggest_size

38905949

1

T1

30141

T2

2544

T3

820

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44444	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

155497

1

T1

8

T2

1

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54108	1			T4	396		T8	24		T20	8
values[0x0]	70173	1			T1	17		T2	1		T3	1
values[0x1]	75660	1			T1	10		T2	1		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34186	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165755

1

T1

9

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	839	1			T4	4		T6	2		T25	10
valid_sources[0x01]	790	1			T4	6		T13	1		T54	4
valid_sources[0x02]	664	1			T4	3		T6	3		T8	1
valid_sources[0x03]	854	1			T4	6		T54	2		T25	7
valid_sources[0x04]	783	1			T4	6		T47	105		T54	2
valid_sources[0x05]	745	1			T2	1		T4	5		T6	3
valid_sources[0x06]	592	1			T4	7		T153	1		T102	1
valid_sources[0x07]	948	1			T4	4		T54	3		T80	1
valid_sources[0x08]	653	1			T4	6		T6	2		T162	2
valid_sources[0x09]	655	1			T4	7		T42	5		T102	1
valid_sources[0x0a]	897	1			T4	3		T73	2		T54	1
valid_sources[0x0b]	850	1			T4	3		T6	1		T20	1
valid_sources[0x0c]	1288	1			T4	8		T24	187		T25	3
valid_sources[0x0d]	779	1			T4	4		T54	6		T25	12
valid_sources[0x0e]	760	1			T4	3		T102	3		T161	1
valid_sources[0x0f]	734	1			T4	9		T26	2		T54	2
valid_sources[0x10]	751	1			T4	5		T20	2		T54	3
valid_sources[0x11]	690	1			T4	9		T54	1		T25	3
valid_sources[0x12]	634	1			T4	6		T54	2		T24	3
valid_sources[0x13]	716	1			T4	6		T6	1		T85	22
valid_sources[0x14]	802	1			T4	9		T54	3		T15	17
valid_sources[0x15]	709	1			T4	5		T6	1		T163	1
valid_sources[0x16]	1236	1			T4	3		T5	1		T8	1
valid_sources[0x17]	810	1			T4	4		T54	3		T25	5
valid_sources[0x18]	616	1			T4	6		T46	1		T10	13
valid_sources[0x19]	617	1			T4	6		T6	2		T8	1
valid_sources[0x1a]	735	1			T4	10		T164	1		T10	2
valid_sources[0x1b]	703	1			T4	6		T54	4		T25	3
valid_sources[0x1c]	711	1			T4	5		T6	1		T153	1
valid_sources[0x1d]	663	1			T4	8		T6	1		T25	14
valid_sources[0x1e]	636	1			T4	5		T6	1		T54	3
valid_sources[0x1f]	790	1			T4	6		T54	2		T25	5
valid_sources[0x20]	1035	1			T4	3		T20	1		T54	4
valid_sources[0x21]	832	1			T4	7		T6	3		T8	1
valid_sources[0x22]	739	1			T4	10		T71	1		T54	2
valid_sources[0x23]	688	1			T4	4		T6	1		T54	4
valid_sources[0x24]	659	1			T4	6		T153	1		T162	1
valid_sources[0x25]	741	1			T4	10		T6	1		T54	1
valid_sources[0x26]	676	1			T11	1		T4	5		T6	1
valid_sources[0x27]	732	1			T4	3		T6	4		T54	2
valid_sources[0x28]	749	1			T4	2		T25	2		T51	19
valid_sources[0x29]	676	1			T4	13		T26	2		T162	1
valid_sources[0x2a]	753	1			T4	7		T54	1		T80	1
valid_sources[0x2b]	970	1			T4	4		T54	2		T25	4
valid_sources[0x2c]	795	1			T4	6		T20	1		T54	2
valid_sources[0x2d]	1243	1			T4	3		T6	5		T20	4
valid_sources[0x2e]	839	1			T4	6		T54	4		T25	4
valid_sources[0x2f]	818	1			T4	5		T10	6		T25	4
valid_sources[0x30]	842	1			T4	5		T44	3		T54	4
valid_sources[0x31]	670	1			T4	4		T153	1		T54	1
valid_sources[0x32]	826	1			T4	6		T6	1		T8	1
valid_sources[0x33]	1222	1			T4	3		T44	1		T54	3
valid_sources[0x34]	891	1			T4	6		T6	2		T44	1
valid_sources[0x35]	712	1			T4	4		T6	1		T71	2
valid_sources[0x36]	834	1			T4	2		T6	1		T153	1
valid_sources[0x37]	868	1			T4	7		T71	2		T54	1
valid_sources[0x38]	668	1			T4	5		T6	1		T80	2
valid_sources[0x39]	1036	1			T4	5		T6	2		T54	3
valid_sources[0x3a]	848	1			T4	10		T6	3		T25	8
valid_sources[0x3b]	774	1			T4	6		T6	2		T8	1
valid_sources[0x3c]	672	1			T4	3		T71	2		T54	3
valid_sources[0x3d]	1262	1			T4	5		T54	1		T24	3
valid_sources[0x3e]	704	1			T4	6		T6	1		T72	1
valid_sources[0x3f]	690	1			T4	3		T6	1		T8	1
valid_sources[0x40]	738	1			T4	4		T6	1		T54	2
valid_sources[0x41]	772	1			T4	5		T54	2		T10	2
valid_sources[0x42]	882	1			T4	4		T6	2		T54	2
valid_sources[0x43]	915	1			T11	1		T4	12		T121	2
valid_sources[0x44]	867	1			T4	5		T71	1		T25	8
valid_sources[0x45]	606	1			T4	9		T6	1		T25	5
valid_sources[0x46]	985	1			T4	10		T6	1		T14	1
valid_sources[0x47]	659	1			T4	5		T23	1		T8	1
valid_sources[0x48]	832	1			T4	9		T6	2		T54	4
valid_sources[0x49]	780	1			T4	7		T20	1		T102	1
valid_sources[0x4a]	778	1			T4	8		T6	5		T162	1
valid_sources[0x4b]	1290	1			T4	6		T54	5		T80	1
valid_sources[0x4c]	744	1			T4	6		T54	1		T80	1
valid_sources[0x4d]	922	1			T4	10		T8	1		T54	1
valid_sources[0x4e]	820	1			T4	4		T10	2		T25	2
valid_sources[0x4f]	673	1			T4	7		T102	1		T54	5
valid_sources[0x50]	848	1			T4	6		T14	2		T54	4
valid_sources[0x51]	739	1			T4	4		T6	2		T153	2
valid_sources[0x52]	721	1			T4	6		T6	2		T10	2
valid_sources[0x53]	817	1			T4	4		T6	4		T80	1
valid_sources[0x54]	702	1			T4	4		T153	3		T54	1
valid_sources[0x55]	646	1			T4	7		T5	1		T80	3
valid_sources[0x56]	703	1			T4	3		T6	2		T54	1
valid_sources[0x57]	638	1			T4	3		T6	2		T27	1
valid_sources[0x58]	646	1			T4	10		T20	1		T54	3
valid_sources[0x59]	1125	1			T4	1		T6	3		T23	1
valid_sources[0x5a]	842	1			T4	6		T6	2		T8	1
valid_sources[0x5b]	1236	1			T4	3		T54	2		T80	1
valid_sources[0x5c]	638	1			T4	8		T6	1		T44	3
valid_sources[0x5d]	908	1			T4	5		T64	2		T54	1
valid_sources[0x5e]	915	1			T4	4		T6	2		T20	4
valid_sources[0x5f]	669	1			T4	5		T8	1		T20	1
valid_sources[0x60]	730	1			T4	2		T6	1		T41	2
valid_sources[0x61]	681	1			T4	8		T6	1		T102	1
valid_sources[0x62]	671	1			T4	3		T54	1		T80	1
valid_sources[0x63]	707	1			T4	9		T8	2		T54	1
valid_sources[0x64]	910	1			T4	2		T54	2		T25	7
valid_sources[0x65]	737	1			T4	6		T42	3		T54	2
valid_sources[0x66]	864	1			T4	7		T54	2		T161	3
valid_sources[0x67]	712	1			T4	5		T6	8		T63	1
valid_sources[0x68]	593	1			T4	2		T54	2		T25	5
valid_sources[0x69]	737	1			T4	6		T8	1		T54	5
valid_sources[0x6a]	709	1			T4	10		T6	5		T8	1
valid_sources[0x6b]	731	1			T4	4		T6	2		T54	1
valid_sources[0x6c]	693	1			T4	6		T54	4		T25	5
valid_sources[0x6d]	800	1			T4	2		T6	1		T71	1
valid_sources[0x6e]	610	1			T4	5		T26	1		T102	2
valid_sources[0x6f]	671	1			T4	8		T153	1		T25	9
valid_sources[0x70]	716	1			T2	1		T4	9		T6	1
valid_sources[0x71]	616	1			T4	4		T44	1		T80	1
valid_sources[0x72]	788	1			T42	1		T26	2		T81	2
valid_sources[0x73]	705	1			T4	5		T8	1		T54	2
valid_sources[0x74]	723	1			T4	6		T6	4		T102	1
valid_sources[0x75]	599	1			T4	5		T6	3		T63	3
valid_sources[0x76]	1175	1			T4	2		T6	2		T16	3
valid_sources[0x77]	897	1			T4	7		T153	2		T10	7
valid_sources[0x78]	876	1			T4	5		T102	2		T54	3
valid_sources[0x79]	732	1			T4	8		T6	3		T54	1
valid_sources[0x7a]	782	1			T4	2		T6	1		T54	3
valid_sources[0x7b]	683	1			T4	4		T8	2		T163	1
valid_sources[0x7c]	868	1			T4	3		T6	1		T102	1
valid_sources[0x7d]	885	1			T4	4		T6	1		T80	1
valid_sources[0x7e]	726	1			T4	10		T6	1		T80	2
valid_sources[0x7f]	579	1			T4	8		T6	1		T64	1
valid_sources[0x80]	609	1			T4	6		T8	1		T26	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41651

1

T4

358

T8

10

T20

4

values[0x0]

all_enables

biggest_size

58364

1

T1

5

T4

486

T6

35

values[0x1]

all_enables

biggest_size

55482

1

T1

3

T2

1

T3

1