Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16040981

1

T1

12009

T3

729

T4

2154

full_word

149480150

1

T1

120080

T2

10000

T3

3281

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	165520851	1			T1	132089		T2	10000		T3	4010
auto[TlIntgErrCmd]	85	1			T74	5		T76	1		T140	4
auto[TlIntgErrData]	90	1			T74	7		T75	1		T76	2
auto[TlIntgErrBoth]	105	1			T74	8		T75	9		T76	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79574646

1

T1

66034

T2

4903

T3

2042

auto[1]

85946485

1

T1

66055

T2

5097

T3

1968

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7843208	1			T1	6009		T3	392		T4	428
auto[TlIntgErrNone]	partial	auto[1]	8197516	1			T1	6000		T3	337		T4	1726
auto[TlIntgErrNone]	full_word	auto[0]	71731304	1			T1	60025		T2	4903		T3	1650
auto[TlIntgErrNone]	full_word	auto[1]	77748823	1			T1	60055		T2	5097		T3	1631
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T74	3		T140	1		T145	3
auto[TlIntgErrCmd]	partial	auto[1]	43	1			T74	2		T140	3		T145	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T148	1		T149	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T76	1		T150	1		T151	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T74	2		T76	1		T143	4
auto[TlIntgErrData]	partial	auto[1]	37	1			T74	5		T75	1		T76	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T144	1		T152	1		T150	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T143	1		T141	1		T144	1
auto[TlIntgErrBoth]	partial	auto[0]	45	1			T74	6		T75	3		T76	2
auto[TlIntgErrBoth]	partial	auto[1]	52	1			T74	2		T75	4		T76	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T75	1		T141	1		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T75	1		T140	1		T149	1