Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	836686	1			T7	692		T41	8		T42	6829
auto[1]	10877412	1			T1	23382		T2	4902		T3	2041
auto[2]	656372	1			T7	384		T41	4		T42	6170
auto[3]	10630464	1			T1	23568		T2	5096		T3	1967

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14491350	1			T1	39270		T2	9998		T3	2753
auto[1]	2168612	1			T1	3647		T3	526		T12	13674
auto[2]	2208520	1			T1	3705		T3	620		T12	13304
auto[3]	4132452	1			T1	328		T3	109		T12	1409

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8739350

1

T1

46949

T2

9998

T3

4008

auto[1]

14261584

1

T1

1

T12

163091

T7

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	407009	1			T7	562		T42	5679		T59	75
auto[0]	auto[0]	auto[1]	42103	1			T7	65		T42	539		T59	6
auto[0]	auto[0]	auto[2]	41932	1			T7	62		T41	2		T42	561
auto[0]	auto[0]	auto[3]	73608	1			T7	3		T41	6		T42	50
auto[0]	auto[1]	auto[0]	3002982	1			T1	19525		T2	4902		T3	1406
auto[0]	auto[1]	auto[1]	327673	1			T1	1706		T3	243		T7	764
auto[0]	auto[1]	auto[2]	323060	1			T1	1982		T3	337		T7	441
auto[0]	auto[1]	auto[3]	313794	1			T1	169		T3	55		T7	85
auto[0]	auto[2]	auto[0]	311069	1			T42	5273		T45	12989		T161	4120
auto[0]	auto[2]	auto[1]	36190	1			T42	471		T45	1344		T161	410
auto[0]	auto[2]	auto[2]	35434	1			T7	345		T42	388		T59	25
auto[0]	auto[2]	auto[3]	51481	1			T7	39		T41	4		T42	37
auto[0]	auto[3]	auto[0]	2855134	1			T1	19745		T2	5096		T3	1347
auto[0]	auto[3]	auto[1]	305370	1			T1	1941		T3	283		T7	350
auto[0]	auto[3]	auto[2]	331908	1			T1	1722		T3	283		T7	1023
auto[0]	auto[3]	auto[3]	280603	1			T1	159		T3	54		T7	91
auto[1]	auto[0]	auto[0]	8989	1			T121	598		T122	210		T160	684
auto[1]	auto[0]	auto[1]	40275	1			T121	2661		T122	953		T160	3045
auto[1]	auto[0]	auto[2]	40231	1			T121	2642		T122	960		T160	3015
auto[1]	auto[0]	auto[3]	182539	1			T121	11857		T122	4427		T160	13333
auto[1]	auto[1]	auto[0]	3953084	1			T12	67449		T43	2		T63	68682
auto[1]	auto[1]	auto[1]	703694	1			T12	6933		T7	2		T63	6841
auto[1]	auto[1]	auto[2]	703402	1			T12	6624		T63	6965		T64	5594
auto[1]	auto[1]	auto[3]	1549723	1			T12	684		T63	698		T64	22334
auto[1]	auto[2]	auto[0]	5735	1			T45	1		T121	521		T160	620
auto[1]	auto[2]	auto[1]	25777	1			T42	1		T121	2527		T160	2704
auto[1]	auto[2]	auto[2]	34812	1			T121	1777		T122	851		T160	2648
auto[1]	auto[2]	auto[3]	155874	1			T121	7823		T122	3975		T160	11209
auto[1]	auto[3]	auto[0]	3947348	1			T12	67255		T63	68543		T64	1280
auto[1]	auto[3]	auto[1]	687530	1			T12	6741		T63	6944		T64	5627
auto[1]	auto[3]	auto[2]	697741	1			T1	1		T12	6680		T63	6861
auto[1]	auto[3]	auto[3]	1524830	1			T12	725		T63	682		T64	22556