Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1104473708	232248	0	0
ctrl_regwen_rd_A	1104473708	4118	0	0
exec_rd_A	1104473708	3631	0	0
exec_regwen_rd_A	1104473708	4116	0	0
readback_rd_A	1104473708	3033	0	0
readback_regwen_rd_A	1104473708	2464	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	232248	0	0
T4	31228	2568	0	0
T5	74335	0	0	0
T6	103785	0	0	0
T7	100784	0	0	0
T12	326683	0	0	0
T13	954605	0	0	0
T23	94359	0	0	0
T24	0	1498	0	0
T25	0	1081	0	0
T41	124545	0	0	0
T42	203172	0	0	0
T43	140122	0	0	0
T51	0	16781	0	0
T52	0	11638	0	0
T55	0	3995	0	0
T56	0	6764	0	0
T65	0	12502	0	0
T82	0	2306	0	0
T83	0	3288	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	4118	0	0
T25	27399	86	0	0
T48	0	395	0	0
T55	0	250	0	0
T56	0	442	0	0
T82	0	198	0	0
T104	237070	0	0	0
T123	741153	0	0	0
T126	0	246	0	0
T127	0	118	0	0
T128	0	89	0	0
T129	0	339	0	0
T130	0	452	0	0
T131	33848	0	0	0
T132	33878	0	0	0
T133	78105	0	0	0
T134	74892	0	0	0
T135	72446	0	0	0
T136	67156	0	0	0
T137	616131	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	3631	0	0
T25	27399	89	0	0
T48	0	391	0	0
T55	0	235	0	0
T56	0	462	0	0
T82	0	239	0	0
T104	237070	0	0	0
T123	741153	0	0	0
T126	0	178	0	0
T127	0	92	0	0
T128	0	102	0	0
T129	0	265	0	0
T130	0	348	0	0
T131	33848	0	0	0
T132	33878	0	0	0
T133	78105	0	0	0
T134	74892	0	0	0
T135	72446	0	0	0
T136	67156	0	0	0
T137	616131	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	4116	0	0
T25	27399	130	0	0
T48	0	417	0	0
T55	0	267	0	0
T56	0	554	0	0
T82	0	167	0	0
T104	237070	0	0	0
T123	741153	0	0	0
T126	0	205	0	0
T127	0	149	0	0
T128	0	168	0	0
T129	0	375	0	0
T130	0	411	0	0
T131	33848	0	0	0
T132	33878	0	0	0
T133	78105	0	0	0
T134	74892	0	0	0
T135	72446	0	0	0
T136	67156	0	0	0
T137	616131	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	3033	0	0
T25	27399	75	0	0
T48	0	374	0	0
T55	0	237	0	0
T56	0	443	0	0
T82	0	187	0	0
T104	237070	0	0	0
T123	741153	0	0	0
T126	0	216	0	0
T127	0	119	0	0
T128	0	85	0	0
T129	0	317	0	0
T130	0	360	0	0
T131	33848	0	0	0
T132	33878	0	0	0
T133	78105	0	0	0
T134	74892	0	0	0
T135	72446	0	0	0
T136	67156	0	0	0
T137	616131	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104473708	2464	0	0
T25	27399	53	0	0
T48	0	322	0	0
T55	0	230	0	0
T56	0	395	0	0
T82	0	103	0	0
T104	237070	0	0	0
T123	741153	0	0	0
T126	0	112	0	0
T127	0	89	0	0
T128	0	85	0	0
T129	0	234	0	0
T130	0	322	0	0
T131	33848	0	0	0
T132	33878	0	0	0
T133	78105	0	0	0
T134	74892	0	0	0
T135	72446	0	0	0
T136	67156	0	0	0
T137	616131	0	0	0