Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16125020	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148738896

1

T1

5118

T3

196606

T5

3050

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	81063764	1			T1	1684		T3	65536		T5	1563
values[0x0]	40298455	1			T1	1813		T3	65517		T5	767
values[0x1]	43501697	1			T1	1745		T3	65553		T5	720

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8197865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156666051

1

T1

5179

T3

196606

T5

3050

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	558367	1			T1	29		T4	781		T10	401
valid_sources[0x01]	528518	1			T1	14		T4	722		T10	397
valid_sources[0x02]	538497	1			T1	36		T4	851		T10	380
valid_sources[0x03]	734541	1			T1	24		T4	808		T10	397
valid_sources[0x04]	545830	1			T1	15		T4	797		T10	400
valid_sources[0x05]	558213	1			T1	13		T4	667		T10	362
valid_sources[0x06]	586918	1			T1	20		T4	720		T10	436
valid_sources[0x07]	544552	1			T1	15		T5	4		T4	722
valid_sources[0x08]	530845	1			T1	21		T5	13		T4	774
valid_sources[0x09]	617223	1			T1	18		T4	738		T10	362
valid_sources[0x0a]	552603	1			T1	19		T4	806		T10	376
valid_sources[0x0b]	534143	1			T1	15		T5	7		T4	801
valid_sources[0x0c]	588514	1			T1	34		T4	733		T10	408
valid_sources[0x0d]	585515	1			T1	16		T5	31		T4	711
valid_sources[0x0e]	533849	1			T1	16		T4	816		T10	375
valid_sources[0x0f]	533555	1			T1	16		T4	791		T10	409
valid_sources[0x10]	2043343	1			T1	20		T4	784		T10	394
valid_sources[0x11]	613784	1			T1	17		T4	856		T10	416
valid_sources[0x12]	534431	1			T1	23		T4	735		T10	396
valid_sources[0x13]	738497	1			T1	25		T4	736		T10	397
valid_sources[0x14]	543637	1			T1	23		T4	704		T10	375
valid_sources[0x15]	547403	1			T1	19		T4	764		T10	373
valid_sources[0x16]	534441	1			T1	25		T5	52		T4	810
valid_sources[0x17]	637280	1			T1	23		T5	88		T4	762
valid_sources[0x18]	1454626	1			T1	26		T4	715		T10	356
valid_sources[0x19]	531727	1			T1	30		T4	803		T10	452
valid_sources[0x1a]	542960	1			T1	18		T4	784		T10	374
valid_sources[0x1b]	578386	1			T1	18		T4	882		T10	364
valid_sources[0x1c]	547354	1			T1	17		T4	762		T10	384
valid_sources[0x1d]	550794	1			T1	24		T4	777		T10	442
valid_sources[0x1e]	576137	1			T1	19		T5	124		T4	819
valid_sources[0x1f]	539488	1			T1	26		T4	771		T10	395
valid_sources[0x20]	1225095	1			T1	18		T4	751		T10	403
valid_sources[0x21]	546607	1			T1	15		T4	723		T10	360
valid_sources[0x22]	564585	1			T1	21		T4	745		T10	358
valid_sources[0x23]	532143	1			T1	13		T4	781		T10	386
valid_sources[0x24]	529804	1			T1	13		T4	782		T10	385
valid_sources[0x25]	558469	1			T1	18		T4	701		T10	370
valid_sources[0x26]	541690	1			T1	17		T4	839		T10	355
valid_sources[0x27]	602533	1			T1	24		T4	817		T10	354
valid_sources[0x28]	567024	1			T1	27		T4	802		T10	405
valid_sources[0x29]	579851	1			T1	25		T4	733		T10	396
valid_sources[0x2a]	568239	1			T1	14		T4	763		T10	334
valid_sources[0x2b]	563728	1			T1	24		T4	793		T10	384
valid_sources[0x2c]	753754	1			T1	26		T4	751		T10	353
valid_sources[0x2d]	566135	1			T1	20		T4	727		T10	417
valid_sources[0x2e]	545471	1			T1	17		T4	812		T10	359
valid_sources[0x2f]	546979	1			T1	14		T4	793		T10	382
valid_sources[0x30]	552804	1			T1	23		T5	16		T4	732
valid_sources[0x31]	552471	1			T1	24		T5	17		T4	740
valid_sources[0x32]	592235	1			T1	24		T4	756		T10	390
valid_sources[0x33]	535097	1			T1	21		T5	38		T4	702
valid_sources[0x34]	584657	1			T1	18		T4	755		T10	415
valid_sources[0x35]	567670	1			T1	22		T4	809		T10	374
valid_sources[0x36]	560519	1			T1	15		T4	801		T10	403
valid_sources[0x37]	631589	1			T1	13		T4	734		T10	366
valid_sources[0x38]	610266	1			T1	25		T4	797		T10	385
valid_sources[0x39]	570720	1			T1	18		T4	732		T10	378
valid_sources[0x3a]	538512	1			T1	22		T4	805		T10	355
valid_sources[0x3b]	655287	1			T1	26		T5	8		T4	714
valid_sources[0x3c]	606818	1			T1	17		T4	781		T10	339
valid_sources[0x3d]	542828	1			T1	19		T4	713		T10	379
valid_sources[0x3e]	554867	1			T1	23		T5	97		T4	780
valid_sources[0x3f]	540659	1			T1	18		T4	684		T10	429
valid_sources[0x40]	1884754	1			T1	20		T4	768		T10	381
valid_sources[0x41]	534266	1			T1	16		T4	789		T10	419
valid_sources[0x42]	553239	1			T1	16		T4	798		T10	382
valid_sources[0x43]	532924	1			T1	19		T5	100		T4	770
valid_sources[0x44]	1147247	1			T1	25		T4	801		T10	362
valid_sources[0x45]	668467	1			T1	20		T4	704		T10	414
valid_sources[0x46]	571297	1			T1	24		T5	55		T4	815
valid_sources[0x47]	593325	1			T1	33		T4	740		T10	398
valid_sources[0x48]	546630	1			T1	14		T5	29		T4	774
valid_sources[0x49]	1602991	1			T1	19		T5	79		T4	717
valid_sources[0x4a]	574574	1			T1	14		T5	29		T4	793
valid_sources[0x4b]	599801	1			T1	21		T5	42		T4	782
valid_sources[0x4c]	540676	1			T1	21		T4	759		T10	413
valid_sources[0x4d]	578221	1			T1	22		T4	763		T10	411
valid_sources[0x4e]	536206	1			T1	22		T4	789		T10	397
valid_sources[0x4f]	630961	1			T1	28		T4	876		T10	366
valid_sources[0x50]	546702	1			T1	13		T5	185		T4	780
valid_sources[0x51]	529900	1			T1	32		T4	782		T10	406
valid_sources[0x52]	532409	1			T1	19		T5	26		T4	812
valid_sources[0x53]	544922	1			T1	30		T4	768		T10	375
valid_sources[0x54]	536778	1			T1	19		T4	778		T10	392
valid_sources[0x55]	597297	1			T1	13		T4	678		T10	388
valid_sources[0x56]	545018	1			T1	11		T4	811		T10	389
valid_sources[0x57]	537413	1			T1	18		T4	774		T10	378
valid_sources[0x58]	563309	1			T1	21		T5	46		T4	668
valid_sources[0x59]	550868	1			T1	27		T4	782		T10	379
valid_sources[0x5a]	544234	1			T1	26		T4	779		T10	390
valid_sources[0x5b]	569498	1			T1	32		T4	700		T10	412
valid_sources[0x5c]	638769	1			T1	20		T4	796		T10	399
valid_sources[0x5d]	527024	1			T1	19		T4	795		T10	413
valid_sources[0x5e]	1784201	1			T1	18		T5	6		T4	727
valid_sources[0x5f]	607856	1			T1	17		T4	748		T10	379
valid_sources[0x60]	551760	1			T1	21		T4	736		T10	400
valid_sources[0x61]	557991	1			T1	21		T4	700		T10	368
valid_sources[0x62]	549236	1			T1	16		T4	790		T10	368
valid_sources[0x63]	1783937	1			T1	21		T4	727		T10	384
valid_sources[0x64]	579006	1			T1	21		T4	718		T10	359
valid_sources[0x65]	559517	1			T1	16		T5	11		T4	726
valid_sources[0x66]	525463	1			T1	21		T4	767		T10	377
valid_sources[0x67]	571103	1			T1	15		T4	798		T10	345
valid_sources[0x68]	531722	1			T1	25		T4	736		T10	410
valid_sources[0x69]	1703708	1			T1	29		T5	46		T4	797
valid_sources[0x6a]	527926	1			T1	12		T4	766		T10	392
valid_sources[0x6b]	555927	1			T1	23		T4	720		T10	388
valid_sources[0x6c]	529568	1			T1	19		T4	716		T10	424
valid_sources[0x6d]	591482	1			T1	22		T4	783		T10	396
valid_sources[0x6e]	570767	1			T1	28		T4	702		T10	397
valid_sources[0x6f]	580345	1			T1	22		T5	3		T4	780
valid_sources[0x70]	526012	1			T1	22		T4	632		T10	384
valid_sources[0x71]	556362	1			T1	26		T5	61		T4	734
valid_sources[0x72]	734837	1			T1	23		T4	876		T10	388
valid_sources[0x73]	531974	1			T1	17		T4	786		T10	402
valid_sources[0x74]	569442	1			T1	16		T5	52		T4	838
valid_sources[0x75]	608821	1			T1	27		T4	750		T10	363
valid_sources[0x76]	566137	1			T1	19		T4	806		T10	401
valid_sources[0x77]	574304	1			T1	17		T4	754		T10	400
valid_sources[0x78]	544779	1			T1	23		T5	85		T4	783
valid_sources[0x79]	534486	1			T1	19		T5	2		T4	814
valid_sources[0x7a]	536607	1			T1	20		T4	776		T10	366
valid_sources[0x7b]	548987	1			T1	28		T4	704		T10	395
valid_sources[0x7c]	539526	1			T1	21		T5	107		T4	818
valid_sources[0x7d]	614733	1			T1	16		T4	860		T10	391
valid_sources[0x7e]	546880	1			T1	19		T4	715		T10	371
valid_sources[0x7f]	549810	1			T1	19		T5	15		T4	825
valid_sources[0x80]	538528	1			T1	19		T4	770		T10	334

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

72957732

1

T1

1631

T3

65536

T5

1563

values[0x0]

all_enables

biggest_size

37892957

1

T1

1795

T3

65517

T5

767

values[0x1]

all_enables

biggest_size

37888207

1

T1

1692

T3

65553

T5

720

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44073	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

142065

1

T1

2272

T3

37

T4

59

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	51276	1			T1	633		T26	400		T27	895
values[0x0]	65149	1			T1	839		T2	1		T3	47
values[0x1]	69713	1			T1	958		T2	2		T3	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34539	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151599

1

T1

2358

T3

48

T4

86

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	832	1			T1	3		T4	2		T26	5
valid_sources[0x01]	636	1			T1	13		T4	2		T10	3
valid_sources[0x02]	1166	1			T1	6		T4	1		T10	2
valid_sources[0x03]	797	1			T1	11		T26	1		T27	12
valid_sources[0x04]	709	1			T1	13		T26	4		T27	9
valid_sources[0x05]	798	1			T1	9		T4	2		T10	1
valid_sources[0x06]	616	1			T1	10		T4	1		T10	1
valid_sources[0x07]	511	1			T1	12		T26	3		T27	8
valid_sources[0x08]	537	1			T1	14		T4	1		T10	1
valid_sources[0x09]	718	1			T1	8		T4	1		T20	1
valid_sources[0x0a]	592	1			T1	8		T4	2		T20	1
valid_sources[0x0b]	923	1			T1	8		T10	2		T26	1
valid_sources[0x0c]	970	1			T1	7		T26	2		T27	17
valid_sources[0x0d]	878	1			T1	12		T4	1		T10	2
valid_sources[0x0e]	831	1			T1	11		T4	6		T10	1
valid_sources[0x0f]	1137	1			T1	16		T3	110		T4	1
valid_sources[0x10]	734	1			T10	1		T12	1		T26	5
valid_sources[0x11]	737	1			T1	7		T10	1		T6	3
valid_sources[0x12]	652	1			T1	6		T4	4		T14	14
valid_sources[0x13]	894	1			T1	14		T26	9		T27	9
valid_sources[0x14]	906	1			T1	16		T4	7		T26	8
valid_sources[0x15]	893	1			T1	8		T10	4		T44	1
valid_sources[0x16]	842	1			T1	8		T26	5		T27	8
valid_sources[0x17]	499	1			T1	4		T10	1		T26	7
valid_sources[0x18]	1000	1			T1	11		T4	2		T10	1
valid_sources[0x19]	584	1			T1	3		T26	8		T27	12
valid_sources[0x1a]	897	1			T1	18		T4	5		T26	7
valid_sources[0x1b]	597	1			T1	7		T4	2		T10	3
valid_sources[0x1c]	641	1			T1	15		T26	8		T27	15
valid_sources[0x1d]	584	1			T1	18		T4	1		T26	8
valid_sources[0x1e]	472	1			T1	8		T10	1		T54	2
valid_sources[0x1f]	938	1			T1	14		T4	2		T10	1
valid_sources[0x20]	774	1			T1	7		T10	1		T12	1
valid_sources[0x21]	736	1			T1	11		T4	2		T10	1
valid_sources[0x22]	524	1			T1	16		T10	1		T26	7
valid_sources[0x23]	833	1			T1	12		T10	1		T12	1
valid_sources[0x24]	750	1			T1	6		T10	1		T26	4
valid_sources[0x25]	735	1			T1	19		T26	4		T27	14
valid_sources[0x26]	941	1			T1	9		T10	1		T26	11
valid_sources[0x27]	468	1			T1	13		T26	3		T27	7
valid_sources[0x28]	538	1			T1	3		T4	2		T21	2
valid_sources[0x29]	704	1			T1	8		T26	8		T27	18
valid_sources[0x2a]	635	1			T1	4		T4	1		T10	1
valid_sources[0x2b]	596	1			T1	17		T4	5		T6	5
valid_sources[0x2c]	642	1			T1	9		T4	2		T26	8
valid_sources[0x2d]	585	1			T1	6		T4	2		T10	1
valid_sources[0x2e]	924	1			T1	11		T26	8		T27	11
valid_sources[0x2f]	654	1			T1	6		T10	1		T6	1
valid_sources[0x30]	605	1			T1	8		T4	1		T10	2
valid_sources[0x31]	734	1			T1	7		T11	1		T21	1
valid_sources[0x32]	504	1			T1	1		T2	3		T26	9
valid_sources[0x33]	725	1			T1	6		T26	3		T27	12
valid_sources[0x34]	781	1			T1	14		T10	1		T20	1
valid_sources[0x35]	522	1			T1	12		T12	1		T26	14
valid_sources[0x36]	1121	1			T1	10		T10	1		T26	8
valid_sources[0x37]	802	1			T1	18		T4	3		T10	1
valid_sources[0x38]	755	1			T1	9		T10	1		T6	4
valid_sources[0x39]	751	1			T1	7		T4	2		T10	1
valid_sources[0x3a]	678	1			T1	6		T4	1		T10	1
valid_sources[0x3b]	797	1			T1	14		T12	1		T26	5
valid_sources[0x3c]	685	1			T1	12		T4	2		T26	9
valid_sources[0x3d]	966	1			T1	6		T10	3		T6	1
valid_sources[0x3e]	771	1			T1	4		T4	2		T26	2
valid_sources[0x3f]	491	1			T1	13		T27	12		T148	1
valid_sources[0x40]	589	1			T1	13		T4	1		T11	1
valid_sources[0x41]	675	1			T1	12		T4	1		T13	2
valid_sources[0x42]	1495	1			T1	13		T4	3		T26	4
valid_sources[0x43]	788	1			T1	10		T4	1		T10	1
valid_sources[0x44]	702	1			T1	13		T4	3		T26	9
valid_sources[0x45]	612	1			T1	4		T4	6		T10	1
valid_sources[0x46]	605	1			T1	2		T12	1		T26	6
valid_sources[0x47]	555	1			T1	2		T4	3		T10	1
valid_sources[0x48]	674	1			T1	5		T15	2		T26	5
valid_sources[0x49]	856	1			T1	3		T4	1		T11	1
valid_sources[0x4a]	749	1			T1	11		T4	2		T10	3
valid_sources[0x4b]	709	1			T1	10		T4	1		T10	1
valid_sources[0x4c]	810	1			T1	13		T12	1		T26	9
valid_sources[0x4d]	957	1			T1	4		T11	1		T12	4
valid_sources[0x4e]	1035	1			T1	14		T4	1		T12	1
valid_sources[0x4f]	589	1			T1	2		T4	2		T10	1
valid_sources[0x50]	617	1			T1	11		T10	1		T26	1
valid_sources[0x51]	580	1			T1	18		T27	16		T124	1
valid_sources[0x52]	876	1			T1	10		T4	1		T26	7
valid_sources[0x53]	578	1			T1	8		T10	1		T6	1
valid_sources[0x54]	1008	1			T1	6		T26	12		T27	18
valid_sources[0x55]	681	1			T1	13		T26	4		T27	15
valid_sources[0x56]	509	1			T1	5		T4	2		T26	8
valid_sources[0x57]	696	1			T1	8		T4	5		T6	2
valid_sources[0x58]	835	1			T1	16		T10	1		T6	4
valid_sources[0x59]	621	1			T1	13		T4	2		T11	1
valid_sources[0x5a]	1081	1			T1	15		T4	1		T10	2
valid_sources[0x5b]	523	1			T1	4		T4	1		T12	1
valid_sources[0x5c]	634	1			T1	8		T4	1		T10	1
valid_sources[0x5d]	792	1			T1	10		T10	3		T11	2
valid_sources[0x5e]	566	1			T1	3		T4	1		T10	1
valid_sources[0x5f]	607	1			T1	22		T12	1		T26	7
valid_sources[0x60]	822	1			T1	13		T21	1		T26	5
valid_sources[0x61]	523	1			T1	10		T4	2		T26	4
valid_sources[0x62]	915	1			T1	8		T10	1		T12	1
valid_sources[0x63]	541	1			T1	14		T4	1		T26	5
valid_sources[0x64]	614	1			T1	17		T11	1		T26	9
valid_sources[0x65]	657	1			T1	11		T4	2		T26	6
valid_sources[0x66]	902	1			T1	16		T26	14		T27	9
valid_sources[0x67]	782	1			T1	5		T10	1		T26	4
valid_sources[0x68]	625	1			T1	8		T5	1		T4	1
valid_sources[0x69]	752	1			T1	13		T20	1		T26	2
valid_sources[0x6a]	547	1			T1	11		T4	2		T10	1
valid_sources[0x6b]	577	1			T1	8		T4	3		T10	1
valid_sources[0x6c]	547	1			T1	6		T10	2		T11	1
valid_sources[0x6d]	720	1			T1	7		T10	1		T26	7
valid_sources[0x6e]	596	1			T1	8		T4	1		T10	1
valid_sources[0x6f]	1258	1			T1	7		T21	1		T26	8
valid_sources[0x70]	620	1			T1	10		T26	3		T27	9
valid_sources[0x71]	581	1			T1	16		T26	4		T27	9
valid_sources[0x72]	1046	1			T1	9		T4	1		T26	2
valid_sources[0x73]	801	1			T1	8		T26	10		T27	10
valid_sources[0x74]	755	1			T1	15		T4	1		T10	1
valid_sources[0x75]	545	1			T1	10		T4	2		T12	2
valid_sources[0x76]	981	1			T1	5		T4	2		T10	1
valid_sources[0x77]	715	1			T1	19		T12	1		T26	7
valid_sources[0x78]	767	1			T1	10		T10	1		T26	10
valid_sources[0x79]	564	1			T1	21		T4	2		T10	1
valid_sources[0x7a]	787	1			T1	10		T4	2		T10	1
valid_sources[0x7b]	677	1			T1	7		T26	9		T27	12
valid_sources[0x7c]	569	1			T1	6		T10	1		T6	1
valid_sources[0x7d]	780	1			T1	13		T4	1		T10	3
valid_sources[0x7e]	612	1			T1	14		T10	2		T26	1
valid_sources[0x7f]	740	1			T1	12		T4	1		T10	4
valid_sources[0x80]	774	1			T1	11		T10	1		T26	13

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38788

1

T1

578

T26

376

T27

826

values[0x0]

all_enables

biggest_size

53108

1

T1

825

T3

22

T4

36

values[0x1]

all_enables

biggest_size

50169

1

T1

869

T3

15

T4

23