Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15998614

1

T1

3019

T6

15772

T11

17199

full_word

145606872

1

T1

5469

T3

196606

T5

3050

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	161605256	1			T1	8488		T3	196606		T5	3050
auto[TlIntgErrCmd]	76	1			T62	4		T63	4		T64	5
auto[TlIntgErrData]	73	1			T62	7		T63	3		T64	1
auto[TlIntgErrBoth]	81	1			T62	9		T63	3		T64	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

77751360

1

T1

2373

T3

65536

T5

1563

auto[1]

83854126

1

T1

6115

T3

131070

T5

1487

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7839371	1			T1	663		T6	7815		T11	8605
auto[TlIntgErrNone]	partial	auto[1]	8159033	1			T1	2356		T6	7957		T11	8594
auto[TlIntgErrNone]	full_word	auto[0]	69911892	1			T1	1710		T3	65536		T5	1563
auto[TlIntgErrNone]	full_word	auto[1]	75694960	1			T1	3759		T3	131070		T5	1487
auto[TlIntgErrCmd]	partial	auto[0]	25	1			T62	1		T63	1		T64	1
auto[TlIntgErrCmd]	partial	auto[1]	45	1			T62	3		T63	2		T64	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T63	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T125	1		T131	1		T132	1
auto[TlIntgErrData]	partial	auto[0]	32	1			T62	3		T63	3		T64	1
auto[TlIntgErrData]	partial	auto[1]	33	1			T62	4		T125	1		T126	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T133	2		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	6	1			T128	2		T129	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T62	4		T63	1		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	42	1			T62	5		T63	1		T64	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T63	1		T64	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T134	1		T135	1		-	-