Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	861720	1			T12	379		T13	16		T45	16426
auto[1]	10617828	1			T5	1563		T6	52384		T11	52280
auto[2]	681763	1			T12	181		T13	12		T45	14607
auto[3]	10322218	1			T5	1486		T6	51725		T11	51753

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14024548	1			T5	3049		T6	86741		T11	87136
auto[1]	2128366	1			T6	8292		T11	8016		T12	587
auto[2]	2151219	1			T6	8303		T11	8120		T12	892
auto[3]	4179396	1			T6	773		T11	761		T12	100

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8624629

1

T5

3048

T6

104108

T11

104028

auto[1]

13858900

1

T5

1

T6

1

T11

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	290583	1			T12	298		T13	13		T76	3
auto[0]	auto[0]	auto[1]	29879	1			T12	41		T13	3		T53	7
auto[0]	auto[0]	auto[2]	29841	1			T12	35		T53	7		T76	9
auto[0]	auto[0]	auto[3]	34345	1			T12	5		T53	911		T76	39
auto[0]	auto[1]	auto[0]	3087042	1			T5	1562		T6	43730		T11	43840
auto[0]	auto[1]	auto[1]	326796	1			T6	3900		T11	3774		T12	358
auto[0]	auto[1]	auto[2]	337688	1			T6	4356		T11	4299		T12	195
auto[0]	auto[1]	auto[3]	312062	1			T6	397		T11	364		T12	43
auto[0]	auto[2]	auto[0]	230799	1			T76	2		T144	14265		T8	6
auto[0]	auto[2]	auto[1]	25304	1			T76	2		T144	1450		T8	1
auto[0]	auto[2]	auto[2]	24863	1			T12	171		T13	12		T76	4
auto[0]	auto[2]	auto[3]	24565	1			T12	10		T53	623		T76	43
auto[0]	auto[3]	auto[0]	2931986	1			T5	1486		T6	43010		T11	43292
auto[0]	auto[3]	auto[1]	319967	1			T6	4392		T11	4241		T12	188
auto[0]	auto[3]	auto[2]	332693	1			T6	3947		T11	3821		T12	491
auto[0]	auto[3]	auto[3]	286216	1			T6	376		T11	397		T12	42
auto[1]	auto[0]	auto[0]	15619	1			T45	548		T144	1		T113	112
auto[1]	auto[0]	auto[1]	70977	1			T45	2505		T113	495		T143	2639
auto[1]	auto[0]	auto[2]	70558	1			T45	2358		T113	483		T143	2603
auto[1]	auto[0]	auto[3]	319918	1			T45	11015		T113	2282		T143	12164
auto[1]	auto[1]	auto[0]	3731013	1			T5	1		T6	1		T11	2
auto[1]	auto[1]	auto[1]	673066	1			T11	1		T45	2777		T48	7617
auto[1]	auto[1]	auto[2]	641438	1			T45	1569		T48	7611		T91	9999
auto[1]	auto[1]	auto[3]	1508723	1			T45	12732		T48	789		T91	844
auto[1]	auto[2]	auto[0]	12499	1			T45	325		T143	556		T145	1
auto[1]	auto[2]	auto[1]	56640	1			T45	1465		T143	2427		T146	4739
auto[1]	auto[2]	auto[2]	55603	1			T45	2273		T144	1		T113	469
auto[1]	auto[2]	auto[3]	251490	1			T45	10544		T113	2001		T143	8085
auto[1]	auto[3]	auto[0]	3725007	1			T11	2		T45	127		T48	75285
auto[1]	auto[3]	auto[1]	625737	1			T45	640		T48	7563		T91	9829
auto[1]	auto[3]	auto[2]	658535	1			T45	2698		T48	7552		T91	8790
auto[1]	auto[3]	auto[3]	1442077	1			T45	12522		T48	737		T91	867