Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1075915180	198535	0	0
ctrl_regwen_rd_A	1075915180	4676	0	0
exec_rd_A	1075915180	4521	0	0
exec_regwen_rd_A	1075915180	4681	0	0
readback_rd_A	1075915180	3166	0	0
readback_regwen_rd_A	1075915180	2811	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	198535	0	0
T1	101901	3804	0	0
T2	960	0	0	0
T3	525552	0	0	0
T4	138005	0	0	0
T5	69609	0	0	0
T6	131165	0	0	0
T10	897272	0	0	0
T11	127993	0	0	0
T12	709223	0	0	0
T13	106750	0	0	0
T26	0	1729	0	0
T27	0	4747	0	0
T49	0	3497	0	0
T52	0	4419	0	0
T59	0	7974	0	0
T68	0	2677	0	0
T69	0	7139	0	0
T70	0	7246	0	0
T71	0	4441	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	4676	0	0
T16	1411	0	0	0
T26	64625	103	0	0
T27	155330	323	0	0
T28	281117	0	0	0
T29	453921	0	0	0
T46	156580	0	0	0
T49	0	337	0	0
T51	287430	0	0	0
T68	0	235	0	0
T74	635780	0	0	0
T75	150676	0	0	0
T118	0	146	0	0
T119	0	145	0	0
T120	0	155	0	0
T121	0	368	0	0
T122	0	268	0	0
T123	0	448	0	0
T124	1038	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	4521	0	0
T16	1411	0	0	0
T26	64625	114	0	0
T27	155330	438	0	0
T28	281117	0	0	0
T29	453921	0	0	0
T46	156580	0	0	0
T49	0	278	0	0
T51	287430	0	0	0
T68	0	194	0	0
T74	635780	0	0	0
T75	150676	0	0	0
T118	0	128	0	0
T119	0	92	0	0
T120	0	112	0	0
T121	0	303	0	0
T122	0	288	0	0
T123	0	286	0	0
T124	1038	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	4681	0	0
T16	1411	0	0	0
T26	64625	84	0	0
T27	155330	383	0	0
T28	281117	0	0	0
T29	453921	0	0	0
T46	156580	0	0	0
T49	0	284	0	0
T51	287430	0	0	0
T68	0	183	0	0
T74	635780	0	0	0
T75	150676	0	0	0
T118	0	138	0	0
T119	0	106	0	0
T120	0	131	0	0
T121	0	318	0	0
T122	0	233	0	0
T123	0	440	0	0
T124	1038	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	3166	0	0
T16	1411	0	0	0
T26	64625	96	0	0
T27	155330	329	0	0
T28	281117	0	0	0
T29	453921	0	0	0
T46	156580	0	0	0
T49	0	221	0	0
T51	287430	0	0	0
T68	0	155	0	0
T74	635780	0	0	0
T75	150676	0	0	0
T118	0	198	0	0
T119	0	92	0	0
T120	0	93	0	0
T121	0	272	0	0
T122	0	295	0	0
T123	0	392	0	0
T124	1038	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075915180	2811	0	0
T16	1411	0	0	0
T26	64625	91	0	0
T27	155330	306	0	0
T28	281117	0	0	0
T29	453921	0	0	0
T46	156580	0	0	0
T49	0	244	0	0
T51	287430	0	0	0
T68	0	139	0	0
T74	635780	0	0	0
T75	150676	0	0	0
T118	0	92	0	0
T119	0	62	0	0
T120	0	90	0	0
T121	0	296	0	0
T122	0	183	0	0
T123	0	302	0	0
T124	1038	0	0	0