Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16828638	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

161654426

1

T1

211518

T3

192754

T4

3058

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	87866711	1			T1	116034		T3	105925		T4	1848
values[0x0]	43631518	1			T1	56085		T3	51339		T4	885
values[0x1]	46984835	1			T1	60516		T3	54949		T4	1005

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8556474	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

169926590

1

T1

222084

T3

202549

T4

3392

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	561724	1			T3	869		T5	20		T6	967
valid_sources[0x01]	578279	1			T3	767		T5	98		T11	15491
valid_sources[0x02]	576766	1			T3	907		T5	55		T6	970
valid_sources[0x03]	588406	1			T3	836		T5	42		T6	1014
valid_sources[0x04]	550053	1			T3	680		T5	87		T6	1039
valid_sources[0x05]	547887	1			T3	848		T5	25		T6	846
valid_sources[0x06]	536206	1			T3	821		T5	24		T11	3971
valid_sources[0x07]	568872	1			T3	928		T5	34		T6	1066
valid_sources[0x08]	578244	1			T3	847		T5	36		T6	910
valid_sources[0x09]	551632	1			T3	802		T5	35		T6	936
valid_sources[0x0a]	548621	1			T3	912		T5	47		T6	972
valid_sources[0x0b]	1156405	1			T3	705		T5	46		T6	947
valid_sources[0x0c]	558307	1			T3	793		T5	53		T6	1040
valid_sources[0x0d]	544438	1			T3	898		T5	50		T6	992
valid_sources[0x0e]	582709	1			T3	810		T5	42		T6	928
valid_sources[0x0f]	554583	1			T3	731		T5	41		T6	978
valid_sources[0x10]	531905	1			T3	800		T5	40		T6	1074
valid_sources[0x11]	564608	1			T3	840		T5	23		T6	959
valid_sources[0x12]	624113	1			T3	780		T5	61		T6	1017
valid_sources[0x13]	550203	1			T3	808		T5	7		T6	909
valid_sources[0x14]	549688	1			T3	804		T5	22		T6	1010
valid_sources[0x15]	589386	1			T3	777		T5	2		T6	1011
valid_sources[0x16]	535372	1			T3	847		T5	15		T6	900
valid_sources[0x17]	577240	1			T1	12399		T3	945		T5	26
valid_sources[0x18]	561738	1			T3	959		T5	33		T6	970
valid_sources[0x19]	566139	1			T3	708		T5	40		T6	1046
valid_sources[0x1a]	563098	1			T3	897		T5	24		T6	1018
valid_sources[0x1b]	2212000	1			T3	872		T5	29		T6	989
valid_sources[0x1c]	2213299	1			T3	662		T5	24		T6	941
valid_sources[0x1d]	539591	1			T3	826		T5	46		T6	1044
valid_sources[0x1e]	600822	1			T3	830		T5	46		T6	1000
valid_sources[0x1f]	544366	1			T3	818		T5	38		T6	990
valid_sources[0x20]	540600	1			T3	834		T5	54		T6	1093
valid_sources[0x21]	556376	1			T1	10531		T3	835		T5	26
valid_sources[0x22]	575678	1			T3	799		T5	14		T6	998
valid_sources[0x23]	595904	1			T3	761		T5	35		T6	958
valid_sources[0x24]	567245	1			T3	859		T5	35		T6	950
valid_sources[0x25]	576940	1			T3	846		T5	23		T6	917
valid_sources[0x26]	541011	1			T3	852		T5	91		T6	933
valid_sources[0x27]	556273	1			T3	849		T5	19		T11	9516
valid_sources[0x28]	600728	1			T3	791		T5	44		T6	1080
valid_sources[0x29]	561883	1			T3	934		T5	51		T6	931
valid_sources[0x2a]	681367	1			T3	771		T5	40		T6	1027
valid_sources[0x2b]	946553	1			T3	802		T5	17		T6	1035
valid_sources[0x2c]	558426	1			T3	890		T5	42		T6	1036
valid_sources[0x2d]	554187	1			T3	920		T5	33		T6	999
valid_sources[0x2e]	579381	1			T1	29607		T3	748		T5	40
valid_sources[0x2f]	571232	1			T3	786		T5	24		T6	1000
valid_sources[0x30]	577237	1			T3	856		T5	18		T6	1025
valid_sources[0x31]	541697	1			T3	864		T5	62		T6	990
valid_sources[0x32]	547975	1			T3	909		T5	44		T11	3615
valid_sources[0x33]	611550	1			T3	878		T5	62		T6	938
valid_sources[0x34]	561543	1			T3	835		T5	30		T6	972
valid_sources[0x35]	565646	1			T3	764		T5	33		T6	933
valid_sources[0x36]	552843	1			T3	727		T5	69		T6	912
valid_sources[0x37]	533542	1			T3	880		T5	22		T6	936
valid_sources[0x38]	542670	1			T3	902		T5	50		T6	917
valid_sources[0x39]	557031	1			T3	806		T5	54		T6	1020
valid_sources[0x3a]	561415	1			T3	903		T5	32		T6	971
valid_sources[0x3b]	600927	1			T3	780		T5	39		T6	964
valid_sources[0x3c]	546710	1			T1	1473		T3	783		T5	32
valid_sources[0x3d]	533306	1			T1	2732		T3	852		T5	43
valid_sources[0x3e]	590777	1			T3	675		T5	30		T6	815
valid_sources[0x3f]	980116	1			T3	752		T5	19		T6	977
valid_sources[0x40]	634858	1			T1	10000		T3	757		T5	63
valid_sources[0x41]	567312	1			T3	969		T5	68		T6	984
valid_sources[0x42]	536052	1			T3	869		T5	24		T6	946
valid_sources[0x43]	559131	1			T3	780		T5	27		T6	1040
valid_sources[0x44]	799556	1			T3	896		T5	33		T6	1009
valid_sources[0x45]	585483	1			T3	781		T5	34		T6	1041
valid_sources[0x46]	559585	1			T3	725		T5	27		T6	981
valid_sources[0x47]	542057	1			T3	863		T5	29		T6	856
valid_sources[0x48]	535423	1			T3	952		T5	28		T6	976
valid_sources[0x49]	546959	1			T3	853		T5	77		T6	949
valid_sources[0x4a]	2403845	1			T3	852		T5	57		T6	871
valid_sources[0x4b]	649046	1			T3	780		T5	37		T6	1043
valid_sources[0x4c]	1237718	1			T3	827		T5	52		T6	1016
valid_sources[0x4d]	1319913	1			T3	867		T5	36		T6	1044
valid_sources[0x4e]	733258	1			T3	988		T5	53		T6	992
valid_sources[0x4f]	549233	1			T3	961		T5	56		T6	1059
valid_sources[0x50]	561497	1			T3	890		T5	24		T6	925
valid_sources[0x51]	540310	1			T3	794		T5	38		T6	930
valid_sources[0x52]	1321911	1			T3	824		T5	40		T6	928
valid_sources[0x53]	533891	1			T3	790		T5	147		T6	1049
valid_sources[0x54]	540272	1			T3	864		T5	46		T6	1088
valid_sources[0x55]	585597	1			T3	957		T5	17		T6	997
valid_sources[0x56]	1926932	1			T3	789		T5	54		T6	1020
valid_sources[0x57]	969902	1			T3	907		T5	47		T6	1005
valid_sources[0x58]	541217	1			T3	923		T5	33		T6	946
valid_sources[0x59]	549484	1			T3	816		T5	65		T6	974
valid_sources[0x5a]	2144765	1			T3	825		T5	19		T6	992
valid_sources[0x5b]	565287	1			T3	765		T5	59		T11	23
valid_sources[0x5c]	561875	1			T3	759		T5	44		T6	1070
valid_sources[0x5d]	553724	1			T3	744		T5	73		T6	960
valid_sources[0x5e]	587007	1			T3	809		T5	42		T6	1011
valid_sources[0x5f]	548523	1			T3	815		T5	31		T6	915
valid_sources[0x60]	540646	1			T3	855		T5	63		T6	1000
valid_sources[0x61]	595657	1			T3	813		T5	49		T6	964
valid_sources[0x62]	548774	1			T3	817		T5	26		T6	1050
valid_sources[0x63]	570491	1			T3	768		T5	37		T6	944
valid_sources[0x64]	534288	1			T3	900		T5	30		T6	980
valid_sources[0x65]	559113	1			T3	912		T5	54		T6	945
valid_sources[0x66]	603115	1			T3	848		T5	17		T6	1050
valid_sources[0x67]	546311	1			T3	701		T5	36		T6	990
valid_sources[0x68]	588519	1			T3	885		T5	59		T6	1111
valid_sources[0x69]	571695	1			T3	953		T5	48		T6	1055
valid_sources[0x6a]	549729	1			T1	7457		T3	752		T5	54
valid_sources[0x6b]	550082	1			T1	9237		T3	831		T5	75
valid_sources[0x6c]	586947	1			T3	838		T5	16		T6	911
valid_sources[0x6d]	591255	1			T3	790		T5	78		T6	1051
valid_sources[0x6e]	1572361	1			T3	856		T5	73		T6	979
valid_sources[0x6f]	551170	1			T3	838		T5	22		T6	939
valid_sources[0x70]	571113	1			T3	736		T5	44		T6	921
valid_sources[0x71]	562167	1			T3	861		T5	58		T6	969
valid_sources[0x72]	658028	1			T3	832		T5	39		T6	990
valid_sources[0x73]	730564	1			T3	1003		T5	63		T6	1053
valid_sources[0x74]	559316	1			T3	751		T5	36		T6	996
valid_sources[0x75]	571241	1			T3	850		T5	72		T6	965
valid_sources[0x76]	561077	1			T3	906		T5	10		T6	968
valid_sources[0x77]	564378	1			T3	760		T5	53		T6	1050
valid_sources[0x78]	559420	1			T3	743		T4	1869		T5	45
valid_sources[0x79]	559315	1			T1	6287		T3	874		T5	31
valid_sources[0x7a]	570152	1			T1	2412		T3	771		T5	45
valid_sources[0x7b]	541339	1			T3	737		T5	44		T6	989
valid_sources[0x7c]	545425	1			T3	807		T5	26		T6	978
valid_sources[0x7d]	533440	1			T3	923		T5	50		T6	1034
valid_sources[0x7e]	560005	1			T3	902		T5	22		T6	969
valid_sources[0x7f]	609582	1			T1	72259		T3	774		T5	39
valid_sources[0x80]	601721	1			T3	847		T5	20		T6	1009

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

79406834

1

T1

105435

T3

96189

T4

1509

values[0x0]

all_enables

biggest_size

41119556

1

T1

52984

T3

48374

T4

777

values[0x1]

all_enables

biggest_size

41128036

1

T1

53099

T3

48191

T4

772

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43114	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

151289

1

T1

11

T2

2

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52485	1			T24	410		T30	24		T8	18
values[0x0]	68695	1			T1	13		T2	7		T3	2
values[0x1]	73223	1			T1	25		T2	4		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33510	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160893

1

T1

16

T2

4

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	597	1			T7	1		T44	1		T48	25
valid_sources[0x01]	649	1			T28	3		T50	8		T41	14
valid_sources[0x02]	851	1			T7	2		T28	6		T50	11
valid_sources[0x03]	537	1			T28	4		T50	17		T41	4
valid_sources[0x04]	935	1			T7	3		T25	1		T46	2
valid_sources[0x05]	673	1			T25	1		T28	6		T50	13
valid_sources[0x06]	518	1			T7	1		T24	1		T28	1
valid_sources[0x07]	964	1			T48	2		T28	1		T50	6
valid_sources[0x08]	703	1			T18	4		T48	10		T28	2
valid_sources[0x09]	727	1			T28	7		T50	11		T41	3
valid_sources[0x0a]	631	1			T1	1		T30	1		T46	1
valid_sources[0x0b]	813	1			T18	4		T28	6		T147	1
valid_sources[0x0c]	556	1			T7	1		T24	2		T62	1
valid_sources[0x0d]	585	1			T18	3		T28	6		T50	9
valid_sources[0x0e]	646	1			T7	2		T8	7		T48	10
valid_sources[0x0f]	803	1			T7	1		T24	1		T18	1
valid_sources[0x10]	569	1			T27	1		T28	2		T50	8
valid_sources[0x11]	1037	1			T7	3		T30	1		T28	4
valid_sources[0x12]	813	1			T24	1		T46	1		T28	3
valid_sources[0x13]	779	1			T7	1		T30	1		T48	2
valid_sources[0x14]	1119	1			T3	5		T7	1		T25	1
valid_sources[0x15]	660	1			T7	1		T30	2		T74	11
valid_sources[0x16]	527	1			T7	2		T8	1		T28	6
valid_sources[0x17]	754	1			T7	1		T25	1		T27	1
valid_sources[0x18]	726	1			T7	2		T25	2		T24	3
valid_sources[0x19]	709	1			T24	2		T46	1		T28	1
valid_sources[0x1a]	629	1			T7	3		T28	3		T50	7
valid_sources[0x1b]	664	1			T28	4		T50	12		T41	3
valid_sources[0x1c]	842	1			T27	1		T30	1		T48	4
valid_sources[0x1d]	660	1			T7	4		T81	1		T28	3
valid_sources[0x1e]	779	1			T1	2		T30	1		T28	6
valid_sources[0x1f]	560	1			T7	2		T28	6		T50	13
valid_sources[0x20]	846	1			T74	4		T28	4		T50	10
valid_sources[0x21]	607	1			T12	11		T30	1		T28	2
valid_sources[0x22]	610	1			T25	1		T26	1		T30	1
valid_sources[0x23]	550	1			T7	3		T24	1		T28	7
valid_sources[0x24]	562	1			T7	3		T25	1		T14	1
valid_sources[0x25]	1019	1			T7	1		T28	5		T50	1
valid_sources[0x26]	705	1			T7	2		T18	1		T154	1
valid_sources[0x27]	560	1			T7	3		T28	1		T50	9
valid_sources[0x28]	885	1			T24	43		T30	1		T28	1
valid_sources[0x29]	864	1			T30	1		T28	2		T50	10
valid_sources[0x2a]	1106	1			T7	1		T50	10		T82	11
valid_sources[0x2b]	888	1			T24	1		T46	1		T28	2
valid_sources[0x2c]	568	1			T7	1		T28	1		T29	48
valid_sources[0x2d]	853	1			T28	3		T50	11		T36	2
valid_sources[0x2e]	878	1			T7	3		T27	1		T46	1
valid_sources[0x2f]	622	1			T7	1		T30	1		T28	3
valid_sources[0x30]	623	1			T28	1		T50	11		T19	1
valid_sources[0x31]	846	1			T1	3		T7	1		T24	130
valid_sources[0x32]	666	1			T7	1		T24	1		T30	1
valid_sources[0x33]	960	1			T1	1		T7	2		T74	3
valid_sources[0x34]	812	1			T7	1		T25	1		T46	1
valid_sources[0x35]	619	1			T7	1		T30	2		T28	7
valid_sources[0x36]	860	1			T1	2		T7	4		T27	1
valid_sources[0x37]	604	1			T7	1		T8	1		T46	1
valid_sources[0x38]	597	1			T28	3		T50	17		T82	6
valid_sources[0x39]	688	1			T1	1		T7	3		T27	1
valid_sources[0x3a]	575	1			T4	2		T7	2		T28	6
valid_sources[0x3b]	788	1			T7	2		T48	21		T50	7
valid_sources[0x3c]	672	1			T7	1		T30	2		T8	2
valid_sources[0x3d]	661	1			T7	2		T30	1		T28	3
valid_sources[0x3e]	1082	1			T7	1		T46	1		T48	5
valid_sources[0x3f]	1136	1			T30	1		T28	3		T50	7
valid_sources[0x40]	789	1			T7	1		T30	1		T18	3
valid_sources[0x41]	660	1			T7	3		T27	2		T30	1
valid_sources[0x42]	737	1			T7	5		T27	2		T18	2
valid_sources[0x43]	788	1			T7	1		T28	1		T50	12
valid_sources[0x44]	704	1			T18	1		T28	6		T50	8
valid_sources[0x45]	857	1			T7	3		T9	9		T18	1
valid_sources[0x46]	548	1			T7	2		T18	7		T50	7
valid_sources[0x47]	613	1			T7	1		T154	1		T28	4
valid_sources[0x48]	661	1			T7	5		T18	2		T28	6
valid_sources[0x49]	648	1			T30	2		T18	4		T28	6
valid_sources[0x4a]	627	1			T28	3		T50	10		T19	5
valid_sources[0x4b]	691	1			T30	3		T46	1		T28	7
valid_sources[0x4c]	872	1			T7	1		T46	1		T14	1
valid_sources[0x4d]	752	1			T28	7		T50	6		T19	1
valid_sources[0x4e]	787	1			T7	2		T18	4		T28	6
valid_sources[0x4f]	607	1			T7	1		T28	6		T50	5
valid_sources[0x50]	743	1			T11	25		T28	5		T50	13
valid_sources[0x51]	562	1			T60	2		T30	1		T50	16
valid_sources[0x52]	1226	1			T7	1		T50	5		T22	1
valid_sources[0x53]	697	1			T7	1		T25	1		T24	22
valid_sources[0x54]	647	1			T7	4		T9	1		T28	4
valid_sources[0x55]	640	1			T24	6		T77	1		T46	1
valid_sources[0x56]	1089	1			T24	4		T30	3		T28	6
valid_sources[0x57]	726	1			T7	1		T30	1		T85	1
valid_sources[0x58]	667	1			T7	1		T25	1		T24	101
valid_sources[0x59]	836	1			T7	2		T9	1		T28	4
valid_sources[0x5a]	642	1			T2	1		T7	3		T30	2
valid_sources[0x5b]	1097	1			T30	3		T8	1		T28	3
valid_sources[0x5c]	1017	1			T25	2		T24	2		T28	5
valid_sources[0x5d]	713	1			T25	1		T30	3		T8	4
valid_sources[0x5e]	590	1			T10	11		T28	5		T50	7
valid_sources[0x5f]	616	1			T30	3		T28	9		T50	7
valid_sources[0x60]	599	1			T7	4		T28	2		T50	11
valid_sources[0x61]	896	1			T2	10		T8	1		T28	4
valid_sources[0x62]	633	1			T1	3		T7	1		T28	6
valid_sources[0x63]	515	1			T7	1		T30	2		T50	8
valid_sources[0x64]	672	1			T24	2		T30	1		T8	1
valid_sources[0x65]	786	1			T1	1		T7	3		T8	1
valid_sources[0x66]	558	1			T7	1		T46	2		T74	2
valid_sources[0x67]	603	1			T7	4		T28	5		T50	11
valid_sources[0x68]	848	1			T7	2		T24	143		T9	2
valid_sources[0x69]	691	1			T7	1		T8	5		T154	1
valid_sources[0x6a]	635	1			T7	2		T30	1		T28	3
valid_sources[0x6b]	1143	1			T30	1		T28	4		T50	10
valid_sources[0x6c]	992	1			T1	3		T7	4		T28	1
valid_sources[0x6d]	589	1			T7	2		T28	1		T50	7
valid_sources[0x6e]	658	1			T7	2		T10	7		T28	1
valid_sources[0x6f]	735	1			T30	1		T48	3		T28	5
valid_sources[0x70]	616	1			T8	1		T28	4		T50	8
valid_sources[0x71]	908	1			T7	1		T46	2		T28	1
valid_sources[0x72]	773	1			T7	1		T28	4		T125	5
valid_sources[0x73]	687	1			T7	5		T24	61		T48	6
valid_sources[0x74]	534	1			T50	6		T41	1		T82	7
valid_sources[0x75]	708	1			T26	1		T18	1		T28	7
valid_sources[0x76]	757	1			T28	2		T50	4		T19	2
valid_sources[0x77]	766	1			T74	5		T48	5		T28	1
valid_sources[0x78]	802	1			T7	2		T62	1		T18	5
valid_sources[0x79]	577	1			T24	3		T30	1		T18	6
valid_sources[0x7a]	676	1			T30	2		T14	1		T28	5
valid_sources[0x7b]	737	1			T28	5		T50	13		T20	4
valid_sources[0x7c]	667	1			T28	3		T29	3		T50	18
valid_sources[0x7d]	658	1			T7	1		T25	1		T114	5
valid_sources[0x7e]	1578	1			T7	2		T24	18		T29	202
valid_sources[0x7f]	629	1			T1	1		T6	1		T27	1
valid_sources[0x80]	740	1			T7	2		T46	1		T28	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40336

1

T24

372

T30

16

T8

10

values[0x0]

all_enables

biggest_size

57021

1

T1

4

T2

2

T11

3

values[0x1]

all_enables

biggest_size

53932

1

T1

7

T4

1

T5

1