Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16709039

1

T1

21117

T3

19459

T4

680

full_word

158430458

1

T1

211518

T3

192754

T4

3058

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	175139217	1			T1	232635		T3	212213		T4	3738
auto[TlIntgErrCmd]	98	1			T71	2		T72	7		T73	7
auto[TlIntgErrData]	91	1			T71	5		T72	2		T73	7
auto[TlIntgErrBoth]	91	1			T71	3		T72	11		T73	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84443391

1

T1

116034

T3

105925

T4

1848

auto[1]

90696106

1

T1

116601

T3

106288

T4

1890

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8185850	1			T1	10599		T3	9736		T4	339
auto[TlIntgErrNone]	partial	auto[1]	8522933	1			T1	10518		T3	9723		T4	341
auto[TlIntgErrNone]	full_word	auto[0]	76257413	1			T1	105435		T3	96189		T4	1509
auto[TlIntgErrNone]	full_word	auto[1]	82173021	1			T1	106083		T3	96565		T4	1549
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T71	2		T72	2		T73	4
auto[TlIntgErrCmd]	partial	auto[1]	49	1			T72	4		T73	2		T137	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T73	1		T141	1		T142	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T72	1		T143	1		T138	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T71	2		T72	1		T73	5
auto[TlIntgErrData]	partial	auto[1]	42	1			T71	2		T72	1		T73	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T71	1		T140	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T143	1		T138	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T71	2		T72	4		T73	3
auto[TlIntgErrBoth]	partial	auto[1]	46	1			T71	1		T72	5		T73	3
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T72	1		T144	2		T142	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T72	1		T138	1		T139	1