Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	886545	1			T6	5381		T25	2580		T8	3
auto[1]	11166385	1			T1	62223		T3	88135		T4	1846
auto[2]	695494	1			T6	3862		T25	1033		T8	6
auto[3]	10850813	1			T1	62783		T3	88556		T4	1889

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15138704	1			T1	103564		T3	146927		T4	2510
auto[1]	2196317	1			T1	10206		T3	14344		T4	545
auto[2]	2228590	1			T1	10252		T3	14077		T4	561
auto[3]	4035626	1			T1	984		T3	1343		T4	119

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9703397

1

T1

125003

T3

22

T4

3734

auto[1]

13895840

1

T1

3

T3

176669

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	311035	1			T25	2144		T8	3		T44	234
auto[0]	auto[0]	auto[1]	32096	1			T25	201		T44	24		T18	26
auto[0]	auto[0]	auto[2]	32431	1			T6	1		T25	205		T44	14
auto[0]	auto[0]	auto[3]	67985	1			T25	30		T44	3		T18	2
auto[0]	auto[1]	auto[0]	3566809	1			T1	51413		T3	10		T4	1233
auto[0]	auto[1]	auto[1]	366935	1			T1	5129		T3	2		T4	274
auto[0]	auto[1]	auto[2]	374659	1			T1	5176		T3	2		T4	289
auto[0]	auto[1]	auto[3]	270333	1			T1	504		T4	49		T5	163
auto[0]	auto[2]	auto[0]	233175	1			T25	793		T8	6		T44	261
auto[0]	auto[2]	auto[1]	27575	1			T25	100		T44	24		T114	1
auto[0]	auto[2]	auto[2]	26736	1			T25	125		T44	22		T18	196
auto[0]	auto[2]	auto[3]	50891	1			T25	15		T44	1		T18	17
auto[0]	auto[3]	auto[0]	3380305	1			T1	52148		T3	6		T4	1277
auto[0]	auto[3]	auto[1]	352775	1			T1	5077		T3	1		T4	271
auto[0]	auto[3]	auto[2]	365511	1			T1	5076		T3	1		T4	271
auto[0]	auto[3]	auto[3]	244146	1			T1	480		T4	70		T5	174
auto[1]	auto[0]	auto[0]	14670	1			T6	207		T114	339		T125	1337
auto[1]	auto[0]	auto[1]	65676	1			T6	781		T114	1531		T125	5840
auto[1]	auto[0]	auto[2]	65604	1			T6	737		T114	1550		T125	5866
auto[1]	auto[0]	auto[3]	297048	1			T6	3655		T114	6844		T125	26566
auto[1]	auto[1]	auto[0]	3810973	1			T1	1		T3	73139		T11	1
auto[1]	auto[1]	auto[1]	676138	1			T3	6927		T6	2374		T61	6992
auto[1]	auto[1]	auto[2]	645570	1			T3	7377		T4	1		T6	1436
auto[1]	auto[1]	auto[3]	1454968	1			T3	678		T6	10787		T61	755
auto[1]	auto[2]	auto[0]	10592	1			T114	290		T125	1192		T149	773
auto[1]	auto[2]	auto[1]	47680	1			T114	1412		T150	1		T125	5417
auto[1]	auto[2]	auto[2]	54152	1			T6	708		T114	1276		T125	3803
auto[1]	auto[2]	auto[3]	244693	1			T6	3154		T114	5725		T125	17584
auto[1]	auto[3]	auto[0]	3811145	1			T1	2		T3	73772		T5	1
auto[1]	auto[3]	auto[1]	627442	1			T3	7414		T6	598		T61	7842
auto[1]	auto[3]	auto[2]	663927	1			T3	6697		T6	2286		T61	7083
auto[1]	auto[3]	auto[3]	1405562	1			T3	665		T6	10353		T61	684