Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1093526012	216818	0	0
ctrl_regwen_rd_A	1093526012	3737	0	0
exec_rd_A	1093526012	3621	0	0
exec_regwen_rd_A	1093526012	3826	0	0
readback_rd_A	1093526012	2267	0	0
readback_regwen_rd_A	1093526012	2197	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	216818	0	0
T8	643396	0	0	0
T24	48767	2558	0	0
T28	0	1570	0	0
T29	0	800	0	0
T30	364847	0	0	0
T44	83963	0	0	0
T45	115004	0	0	0
T50	0	3183	0	0
T53	0	4021	0	0
T54	0	7471	0	0
T60	76930	0	0	0
T61	462761	0	0	0
T62	266728	0	0	0
T64	0	12838	0	0
T76	120493	0	0	0
T81	77803	0	0	0
T82	0	1769	0	0
T83	0	1785	0	0
T84	0	1388	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	3737	0	0
T19	581612	0	0	0
T22	818949	0	0	0
T29	13799	51	0	0
T32	33648	0	0	0
T50	147080	0	0	0
T51	0	599	0	0
T67	483898	0	0	0
T68	440054	0	0	0
T69	73685	0	0	0
T70	243126	0	0	0
T82	0	195	0	0
T83	0	104	0	0
T127	0	347	0	0
T128	0	283	0	0
T129	0	100	0	0
T130	0	149	0	0
T131	0	83	0	0
T132	0	56	0	0
T133	86926	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	3621	0	0
T19	581612	0	0	0
T22	818949	0	0	0
T29	13799	42	0	0
T32	33648	0	0	0
T50	147080	0	0	0
T51	0	606	0	0
T67	483898	0	0	0
T68	440054	0	0	0
T69	73685	0	0	0
T70	243126	0	0	0
T82	0	159	0	0
T83	0	55	0	0
T127	0	369	0	0
T128	0	263	0	0
T129	0	146	0	0
T130	0	164	0	0
T131	0	27	0	0
T132	0	64	0	0
T133	86926	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	3826	0	0
T19	581612	0	0	0
T22	818949	0	0	0
T29	13799	49	0	0
T32	33648	0	0	0
T50	147080	0	0	0
T51	0	644	0	0
T67	483898	0	0	0
T68	440054	0	0	0
T69	73685	0	0	0
T70	243126	0	0	0
T82	0	187	0	0
T83	0	78	0	0
T127	0	240	0	0
T128	0	307	0	0
T129	0	120	0	0
T130	0	152	0	0
T131	0	46	0	0
T132	0	52	0	0
T133	86926	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	2267	0	0
T19	581612	0	0	0
T22	818949	0	0	0
T29	13799	37	0	0
T32	33648	0	0	0
T50	147080	0	0	0
T51	0	575	0	0
T67	483898	0	0	0
T68	440054	0	0	0
T69	73685	0	0	0
T70	243126	0	0	0
T82	0	131	0	0
T83	0	89	0	0
T127	0	339	0	0
T128	0	201	0	0
T129	0	119	0	0
T130	0	134	0	0
T131	0	26	0	0
T132	0	52	0	0
T133	86926	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1093526012	2197	0	0
T19	581612	0	0	0
T22	818949	0	0	0
T29	13799	47	0	0
T32	33648	0	0	0
T50	147080	0	0	0
T51	0	613	0	0
T67	483898	0	0	0
T68	440054	0	0	0
T69	73685	0	0	0
T70	243126	0	0	0
T82	0	158	0	0
T83	0	66	0	0
T127	0	203	0	0
T128	0	258	0	0
T129	0	134	0	0
T130	0	181	0	0
T131	0	23	0	0
T132	0	47	0	0
T133	86926	0	0	0