Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15892691	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

157761516

1

T1

1537

T2

1055

T3

6060

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85596954	1			T1	14954		T2	2895		T3	3379
values[0x0]	42455182	1			T1	4905		T2	999		T3	1653
values[0x1]	45602071	1			T1	10550		T2	1953		T3	1655

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8085920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165568287

1

T1

13800

T2

3434

T3

6382

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	570159	1			T1	65		T2	15		T3	36
valid_sources[0x01]	653288	1			T1	130		T2	13		T3	20
valid_sources[0x02]	539985	1			T1	94		T2	16		T3	15
valid_sources[0x03]	587377	1			T1	178		T2	9		T3	23
valid_sources[0x04]	561250	1			T1	272		T2	29		T3	21
valid_sources[0x05]	563065	1			T1	57		T2	14		T3	24
valid_sources[0x06]	563633	1			T1	130		T2	20		T3	19
valid_sources[0x07]	675115	1			T1	41		T2	28		T3	29
valid_sources[0x08]	539183	1			T1	96		T2	18		T3	12
valid_sources[0x09]	538144	1			T1	101		T2	16		T3	21
valid_sources[0x0a]	610323	1			T1	110		T2	20		T3	32
valid_sources[0x0b]	609224	1			T1	211		T2	18		T3	21
valid_sources[0x0c]	531979	1			T1	81		T2	16		T3	25
valid_sources[0x0d]	556977	1			T1	57		T2	23		T3	25
valid_sources[0x0e]	577301	1			T1	112		T2	32		T3	26
valid_sources[0x0f]	543473	1			T1	132		T2	45		T3	32
valid_sources[0x10]	530288	1			T1	68		T2	28		T3	29
valid_sources[0x11]	597242	1			T1	88		T2	24		T3	20
valid_sources[0x12]	563616	1			T1	138		T2	13		T3	20
valid_sources[0x13]	569696	1			T1	152		T2	32		T3	22
valid_sources[0x14]	592039	1			T1	149		T2	25		T3	16
valid_sources[0x15]	618042	1			T1	97		T2	31		T3	28
valid_sources[0x16]	743813	1			T1	147		T2	11		T3	31
valid_sources[0x17]	556915	1			T1	95		T2	26		T3	21
valid_sources[0x18]	604041	1			T1	31		T2	24		T3	25
valid_sources[0x19]	584063	1			T1	83		T2	15		T3	28
valid_sources[0x1a]	571023	1			T1	193		T2	15		T3	31
valid_sources[0x1b]	551708	1			T1	142		T2	23		T3	50
valid_sources[0x1c]	538623	1			T1	183		T2	20		T3	19
valid_sources[0x1d]	538813	1			T1	36		T2	12		T3	12
valid_sources[0x1e]	580356	1			T1	219		T2	33		T3	44
valid_sources[0x1f]	583544	1			T1	75		T2	24		T3	21
valid_sources[0x20]	552415	1			T1	82		T2	23		T3	26
valid_sources[0x21]	579901	1			T1	104		T2	29		T3	18
valid_sources[0x22]	530113	1			T1	161		T2	44		T3	27
valid_sources[0x23]	544038	1			T1	211		T2	16		T3	19
valid_sources[0x24]	583312	1			T1	113		T2	19		T3	27
valid_sources[0x25]	604466	1			T1	129		T2	33		T3	45
valid_sources[0x26]	562062	1			T1	138		T2	29		T3	36
valid_sources[0x27]	1556569	1			T1	72		T2	26		T3	26
valid_sources[0x28]	530452	1			T1	155		T2	33		T3	26
valid_sources[0x29]	596113	1			T1	51		T2	33		T3	22
valid_sources[0x2a]	592742	1			T1	65		T2	32		T3	30
valid_sources[0x2b]	555102	1			T1	116		T2	20		T3	15
valid_sources[0x2c]	551047	1			T1	199		T2	23		T3	24
valid_sources[0x2d]	633544	1			T1	104		T2	26		T3	12
valid_sources[0x2e]	568900	1			T1	74		T2	20		T3	22
valid_sources[0x2f]	641188	1			T1	248		T2	31		T3	33
valid_sources[0x30]	559316	1			T1	84		T2	28		T3	21
valid_sources[0x31]	601070	1			T1	52		T2	18		T3	26
valid_sources[0x32]	617239	1			T1	82		T2	18		T3	22
valid_sources[0x33]	555364	1			T1	124		T2	23		T3	22
valid_sources[0x34]	555457	1			T1	216		T2	34		T3	18
valid_sources[0x35]	553437	1			T1	33		T2	34		T3	26
valid_sources[0x36]	618017	1			T1	159		T2	28		T3	28
valid_sources[0x37]	756349	1			T1	77		T2	40		T3	31
valid_sources[0x38]	536876	1			T1	51		T2	35		T3	41
valid_sources[0x39]	533971	1			T1	94		T2	27		T3	19
valid_sources[0x3a]	540956	1			T1	85		T2	23		T3	27
valid_sources[0x3b]	598212	1			T1	155		T2	12		T3	25
valid_sources[0x3c]	595488	1			T1	207		T2	25		T3	23
valid_sources[0x3d]	581516	1			T1	59		T2	20		T3	30
valid_sources[0x3e]	568154	1			T1	143		T2	17		T3	32
valid_sources[0x3f]	533087	1			T1	121		T2	23		T3	22
valid_sources[0x40]	649388	1			T1	96		T2	27		T3	24
valid_sources[0x41]	630371	1			T1	95		T2	21		T3	21
valid_sources[0x42]	623871	1			T1	116		T2	29		T3	17
valid_sources[0x43]	624574	1			T1	101		T2	16		T3	31
valid_sources[0x44]	571926	1			T1	210		T2	35		T3	36
valid_sources[0x45]	537712	1			T1	76		T2	7		T3	20
valid_sources[0x46]	581412	1			T1	124		T2	16		T3	31
valid_sources[0x47]	566264	1			T1	92		T2	17		T3	27
valid_sources[0x48]	579353	1			T1	134		T2	32		T3	22
valid_sources[0x49]	3039482	1			T1	75		T2	17		T3	29
valid_sources[0x4a]	535947	1			T1	132		T2	18		T3	37
valid_sources[0x4b]	544205	1			T1	184		T2	13		T3	40
valid_sources[0x4c]	573274	1			T1	110		T2	22		T3	30
valid_sources[0x4d]	553680	1			T1	177		T2	14		T3	22
valid_sources[0x4e]	614476	1			T1	105		T2	16		T3	26
valid_sources[0x4f]	585227	1			T1	100		T2	27		T3	29
valid_sources[0x50]	532884	1			T1	120		T2	19		T3	34
valid_sources[0x51]	2026029	1			T1	104		T2	24		T3	31
valid_sources[0x52]	552178	1			T1	111		T2	9		T3	29
valid_sources[0x53]	581435	1			T1	93		T2	33		T3	16
valid_sources[0x54]	555122	1			T1	108		T2	23		T3	25
valid_sources[0x55]	566539	1			T1	226		T2	17		T3	24
valid_sources[0x56]	546217	1			T1	269		T2	12		T3	22
valid_sources[0x57]	564226	1			T1	145		T2	18		T3	26
valid_sources[0x58]	569257	1			T1	216		T2	14		T3	34
valid_sources[0x59]	573604	1			T1	215		T2	24		T3	28
valid_sources[0x5a]	590940	1			T1	39		T2	25		T3	37
valid_sources[0x5b]	568835	1			T1	175		T2	18		T3	32
valid_sources[0x5c]	538641	1			T1	96		T2	11		T3	29
valid_sources[0x5d]	547357	1			T1	104		T2	23		T3	19
valid_sources[0x5e]	588553	1			T1	97		T2	19		T3	33
valid_sources[0x5f]	571701	1			T1	86		T2	27		T3	26
valid_sources[0x60]	666382	1			T1	133		T2	31		T3	30
valid_sources[0x61]	565498	1			T1	55		T2	29		T3	24
valid_sources[0x62]	603333	1			T1	97		T2	26		T3	26
valid_sources[0x63]	539601	1			T1	141		T2	18		T3	24
valid_sources[0x64]	536487	1			T1	85		T2	28		T3	17
valid_sources[0x65]	552931	1			T1	49		T2	38		T3	10
valid_sources[0x66]	597839	1			T1	83		T2	25		T3	32
valid_sources[0x67]	537873	1			T1	174		T2	26		T3	18
valid_sources[0x68]	549937	1			T1	122		T2	36		T3	28
valid_sources[0x69]	576424	1			T1	161		T2	27		T3	20
valid_sources[0x6a]	561920	1			T1	104		T2	28		T3	23
valid_sources[0x6b]	546783	1			T1	88		T2	21		T3	20
valid_sources[0x6c]	555174	1			T1	101		T2	41		T3	26
valid_sources[0x6d]	602948	1			T1	29		T2	27		T3	19
valid_sources[0x6e]	584920	1			T1	129		T2	20		T3	22
valid_sources[0x6f]	541984	1			T1	169		T2	19		T3	28
valid_sources[0x70]	574057	1			T1	125		T2	17		T3	32
valid_sources[0x71]	1079109	1			T1	162		T2	25		T3	33
valid_sources[0x72]	556076	1			T1	170		T2	27		T3	22
valid_sources[0x73]	553976	1			T1	185		T2	37		T3	24
valid_sources[0x74]	573968	1			T1	101		T2	25		T3	28
valid_sources[0x75]	548870	1			T1	147		T2	25		T3	12
valid_sources[0x76]	556180	1			T1	74		T2	40		T3	14
valid_sources[0x77]	574838	1			T1	42		T2	27		T3	20
valid_sources[0x78]	542125	1			T1	69		T2	21		T3	41
valid_sources[0x79]	585695	1			T1	23		T2	28		T3	23
valid_sources[0x7a]	569938	1			T1	146		T2	16		T3	20
valid_sources[0x7b]	590908	1			T1	62		T2	24		T3	26
valid_sources[0x7c]	536376	1			T1	99		T2	25		T3	27
valid_sources[0x7d]	2994794	1			T1	124		T2	17		T3	31
valid_sources[0x7e]	930940	1			T1	122		T2	26		T3	24
valid_sources[0x7f]	544295	1			T1	68		T2	23		T3	35
valid_sources[0x80]	554040	1			T1	80		T2	23		T3	39

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77608967

1

T1

131

T2

531

T3

3041

values[0x0]

all_enables

biggest_size

40083611

1

T1

716

T2

237

T3

1570

values[0x1]

all_enables

biggest_size

40068938

1

T1

690

T2

287

T3

1449

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44076	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

145819

1

T2

1

T3

1

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52097	1			T23	11		T24	17		T26	588
values[0x0]	66591	1			T2	1		T3	1		T7	2
values[0x1]	71207	1			T1	3		T2	1		T7	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34340	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155555

1

T1

1

T2

1

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	718	1			T23	2		T28	2		T16	1
valid_sources[0x01]	708	1			T14	3		T23	1		T26	11
valid_sources[0x02]	1215	1			T13	1		T23	1		T26	7
valid_sources[0x03]	857	1			T13	4		T63	1		T22	1
valid_sources[0x04]	625	1			T24	2		T26	9		T25	1
valid_sources[0x05]	659	1			T59	6		T26	8		T9	1
valid_sources[0x06]	750	1			T23	1		T28	3		T26	5
valid_sources[0x07]	691	1			T24	1		T26	6		T157	1
valid_sources[0x08]	704	1			T26	4		T25	1		T84	1
valid_sources[0x09]	806	1			T23	1		T26	8		T71	2
valid_sources[0x0a]	684	1			T66	1		T26	6		T25	1
valid_sources[0x0b]	728	1			T23	1		T73	2		T26	3
valid_sources[0x0c]	625	1			T45	1		T26	12		T25	1
valid_sources[0x0d]	649	1			T11	1		T26	10		T25	2
valid_sources[0x0e]	548	1			T45	1		T28	2		T24	1
valid_sources[0x0f]	829	1			T16	2		T26	8		T25	1
valid_sources[0x10]	759	1			T15	2		T45	1		T26	20
valid_sources[0x11]	1020	1			T14	1		T23	1		T26	14
valid_sources[0x12]	737	1			T26	2		T10	4		T156	1
valid_sources[0x13]	563	1			T11	2		T26	8		T71	1
valid_sources[0x14]	709	1			T23	2		T24	3		T26	7
valid_sources[0x15]	798	1			T22	1		T73	1		T26	7
valid_sources[0x16]	910	1			T12	1		T26	12		T71	3
valid_sources[0x17]	781	1			T23	1		T45	1		T75	1
valid_sources[0x18]	687	1			T45	1		T26	17		T86	2
valid_sources[0x19]	670	1			T158	8		T26	3		T71	1
valid_sources[0x1a]	1020	1			T14	1		T45	1		T26	14
valid_sources[0x1b]	775	1			T14	10		T26	5		T10	1
valid_sources[0x1c]	870	1			T13	1		T26	7		T9	3
valid_sources[0x1d]	629	1			T23	2		T45	1		T71	3
valid_sources[0x1e]	643	1			T23	1		T26	3		T71	1
valid_sources[0x1f]	692	1			T23	1		T26	7		T71	1
valid_sources[0x20]	608	1			T47	3		T23	1		T75	1
valid_sources[0x21]	772	1			T15	1		T24	2		T26	8
valid_sources[0x22]	934	1			T14	3		T26	5		T84	2
valid_sources[0x23]	741	1			T23	1		T26	12		T71	1
valid_sources[0x24]	561	1			T26	9		T157	1		T71	1
valid_sources[0x25]	820	1			T47	3		T26	7		T25	1
valid_sources[0x26]	588	1			T13	1		T15	2		T16	3
valid_sources[0x27]	773	1			T26	5		T9	1		T71	2
valid_sources[0x28]	567	1			T26	9		T9	1		T29	15
valid_sources[0x29]	597	1			T24	1		T26	8		T25	2
valid_sources[0x2a]	781	1			T24	2		T26	14		T65	1
valid_sources[0x2b]	642	1			T26	10		T159	1		T10	1
valid_sources[0x2c]	645	1			T28	1		T26	6		T71	1
valid_sources[0x2d]	880	1			T13	1		T22	1		T26	10
valid_sources[0x2e]	757	1			T11	1		T13	2		T24	1
valid_sources[0x2f]	644	1			T26	6		T25	1		T160	1
valid_sources[0x30]	769	1			T26	14		T9	1		T157	1
valid_sources[0x31]	638	1			T26	13		T9	2		T161	1
valid_sources[0x32]	731	1			T23	1		T26	10		T25	1
valid_sources[0x33]	869	1			T23	1		T26	8		T9	3
valid_sources[0x34]	629	1			T23	1		T26	5		T100	3
valid_sources[0x35]	604	1			T15	2		T26	3		T71	1
valid_sources[0x36]	986	1			T23	1		T45	1		T28	1
valid_sources[0x37]	759	1			T26	11		T71	1		T10	1
valid_sources[0x38]	618	1			T47	2		T26	6		T71	1
valid_sources[0x39]	674	1			T73	3		T26	4		T25	1
valid_sources[0x3a]	724	1			T74	1		T26	10		T10	2
valid_sources[0x3b]	836	1			T26	13		T9	1		T10	13
valid_sources[0x3c]	758	1			T47	5		T45	1		T26	3
valid_sources[0x3d]	797	1			T14	1		T26	8		T10	3
valid_sources[0x3e]	686	1			T28	2		T24	1		T26	3
valid_sources[0x3f]	732	1			T13	1		T27	1		T23	1
valid_sources[0x40]	647	1			T11	2		T14	2		T26	9
valid_sources[0x41]	691	1			T16	1		T26	3		T157	1
valid_sources[0x42]	618	1			T27	1		T24	5		T26	12
valid_sources[0x43]	697	1			T26	7		T9	1		T71	1
valid_sources[0x44]	635	1			T24	4		T26	10		T84	1
valid_sources[0x45]	619	1			T47	1		T26	5		T71	2
valid_sources[0x46]	792	1			T24	4		T26	5		T25	1
valid_sources[0x47]	710	1			T14	2		T26	6		T84	2
valid_sources[0x48]	927	1			T47	6		T84	1		T71	3
valid_sources[0x49]	585	1			T47	2		T24	2		T26	12
valid_sources[0x4a]	656	1			T28	4		T24	1		T26	2
valid_sources[0x4b]	702	1			T16	1		T26	2		T71	1
valid_sources[0x4c]	709	1			T47	1		T24	1		T26	8
valid_sources[0x4d]	637	1			T26	13		T25	1		T84	1
valid_sources[0x4e]	659	1			T13	1		T15	1		T16	1
valid_sources[0x4f]	611	1			T28	1		T26	5		T71	1
valid_sources[0x50]	869	1			T26	10		T10	1		T29	3
valid_sources[0x51]	625	1			T28	2		T24	3		T26	11
valid_sources[0x52]	623	1			T26	5		T84	2		T9	1
valid_sources[0x53]	749	1			T45	1		T24	4		T26	3
valid_sources[0x54]	727	1			T11	1		T24	1		T26	14
valid_sources[0x55]	630	1			T23	1		T26	17		T25	1
valid_sources[0x56]	885	1			T26	14		T25	2		T9	1
valid_sources[0x57]	680	1			T45	1		T24	1		T26	12
valid_sources[0x58]	610	1			T23	1		T26	3		T10	1
valid_sources[0x59]	613	1			T26	17		T71	1		T10	4
valid_sources[0x5a]	583	1			T24	2		T26	8		T9	1
valid_sources[0x5b]	827	1			T45	1		T73	3		T26	5
valid_sources[0x5c]	596	1			T7	1		T23	1		T26	3
valid_sources[0x5d]	679	1			T23	1		T26	13		T25	1
valid_sources[0x5e]	711	1			T24	3		T26	11		T25	1
valid_sources[0x5f]	725	1			T24	1		T26	7		T10	2
valid_sources[0x60]	680	1			T13	1		T26	14		T162	1
valid_sources[0x61]	1043	1			T23	1		T26	4		T82	1
valid_sources[0x62]	643	1			T11	1		T15	1		T24	4
valid_sources[0x63]	662	1			T23	1		T26	12		T9	1
valid_sources[0x64]	689	1			T26	8		T25	1		T71	2
valid_sources[0x65]	836	1			T24	1		T26	3		T71	3
valid_sources[0x66]	663	1			T24	2		T26	3		T9	1
valid_sources[0x67]	676	1			T26	10		T10	2		T29	3
valid_sources[0x68]	914	1			T26	4		T71	2		T10	2
valid_sources[0x69]	901	1			T11	1		T5	1		T26	6
valid_sources[0x6a]	582	1			T24	1		T26	7		T71	1
valid_sources[0x6b]	735	1			T24	3		T26	14		T71	1
valid_sources[0x6c]	676	1			T45	2		T26	17		T71	1
valid_sources[0x6d]	591	1			T13	1		T26	13		T18	1
valid_sources[0x6e]	644	1			T26	5		T9	2		T10	2
valid_sources[0x6f]	972	1			T26	2		T156	1		T160	1
valid_sources[0x70]	865	1			T24	1		T26	7		T71	1
valid_sources[0x71]	628	1			T22	1		T26	9		T51	1
valid_sources[0x72]	694	1			T26	10		T9	1		T71	1
valid_sources[0x73]	1286	1			T23	1		T24	1		T26	6
valid_sources[0x74]	862	1			T26	7		T71	1		T10	2
valid_sources[0x75]	887	1			T24	1		T26	3		T25	1
valid_sources[0x76]	653	1			T13	1		T14	1		T47	3
valid_sources[0x77]	788	1			T4	2		T45	1		T24	1
valid_sources[0x78]	671	1			T14	4		T26	6		T10	3
valid_sources[0x79]	724	1			T26	16		T65	4		T10	10
valid_sources[0x7a]	650	1			T11	1		T13	1		T45	1
valid_sources[0x7b]	713	1			T26	4		T157	1		T10	1
valid_sources[0x7c]	930	1			T15	2		T24	1		T26	8
valid_sources[0x7d]	619	1			T26	14		T25	1		T38	2
valid_sources[0x7e]	988	1			T26	7		T163	1		T18	2
valid_sources[0x7f]	789	1			T24	1		T26	4		T9	1
valid_sources[0x80]	801	1			T47	4		T74	1		T26	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

38962

1

T23

4

T24

11

T26

534

values[0x0]

all_enables

biggest_size

54762

1

T2

1

T3

1

T4

1

values[0x1]

all_enables

biggest_size

52095

1

T11

2

T5

1

T12

1