Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15775598

1

T1

28872

T2

4792

T3

627

full_word

154658320

1

T1

1537

T2

1055

T3

6060

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	170433588	1			T1	30409		T2	5847		T3	6687
auto[TlIntgErrCmd]	92	1			T60	3		T61	4		T62	8
auto[TlIntgErrData]	115	1			T60	5		T61	5		T62	8
auto[TlIntgErrBoth]	123	1			T60	2		T61	11		T62	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82295181

1

T1

14954

T2

2895

T3

3379

auto[1]

88138737

1

T1

15455

T2

2952

T3

3308

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7722986	1			T1	14823		T2	2364		T3	338
auto[TlIntgErrNone]	partial	auto[1]	8052308	1			T1	14049		T2	2428		T3	289
auto[TlIntgErrNone]	full_word	auto[0]	74572054	1			T1	131		T2	531		T3	3041
auto[TlIntgErrNone]	full_word	auto[1]	80086240	1			T1	1406		T2	524		T3	3019
auto[TlIntgErrCmd]	partial	auto[0]	32	1			T60	1		T61	1		T62	2
auto[TlIntgErrCmd]	partial	auto[1]	50	1			T60	2		T61	3		T62	6
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T137	1		T138	1		T145	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T139	1		T146	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T60	3		T61	3		T62	2
auto[TlIntgErrData]	partial	auto[1]	51	1			T60	1		T61	2		T62	5
auto[TlIntgErrData]	full_word	auto[0]	4	1			T139	1		T135	1		T148	2
auto[TlIntgErrData]	full_word	auto[1]	4	1			T60	1		T62	1		T139	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T60	2		T61	2		T136	4
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T61	7		T62	4		T137	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T139	2		T140	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T61	2		T135	1		T149	1