Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	913767	1			T4	1250		T5	579		T6	2
auto[1]	10211488	1			T2	15		T3	3354		T7	129454
auto[2]	685954	1			T4	1063		T5	368		T27	7
auto[3]	9938215	1			T2	15		T3	3281		T7	129177

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13681233	1			T3	5515		T7	213716		T4	73
auto[1]	2048464	1			T2	3		T3	500		T7	21307
auto[2]	2077888	1			T2	4		T3	557		T7	21551
auto[3]	3941839	1			T2	23		T3	63		T7	2057

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8905811

1

T2

30

T3

6635

T4

4264

auto[1]

12843613

1

T7

258631

T97

2

T59

189209

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	362484	1			T4	37		T5	474		T6	1
auto[0]	auto[0]	auto[1]	37560	1			T4	194		T5	49		T6	1
auto[0]	auto[0]	auto[2]	37967	1			T4	182		T5	48		T27	1
auto[0]	auto[0]	auto[3]	63440	1			T4	837		T5	8		T27	8
auto[0]	auto[1]	auto[0]	3152241	1			T3	2776		T4	5		T11	5380
auto[0]	auto[1]	auto[1]	332946	1			T2	1		T3	243		T4	182
auto[0]	auto[1]	auto[2]	338068	1			T2	2		T3	300		T4	33
auto[0]	auto[1]	auto[3]	300613	1			T2	12		T3	35		T4	859
auto[0]	auto[2]	auto[0]	251358	1			T4	31		T5	286		T97	13
auto[0]	auto[2]	auto[1]	28880	1			T4	184		T5	28		T97	662
auto[0]	auto[2]	auto[2]	27467	1			T4	164		T5	52		T27	1
auto[0]	auto[2]	auto[3]	45809	1			T4	684		T5	2		T27	6
auto[0]	auto[3]	auto[0]	3001867	1			T3	2739		T11	3448		T5	144
auto[0]	auto[3]	auto[1]	319516	1			T2	2		T3	257		T4	13
auto[0]	auto[3]	auto[2]	335382	1			T2	2		T3	257		T4	148
auto[0]	auto[3]	auto[3]	270213	1			T2	11		T3	28		T4	711
auto[1]	auto[0]	auto[0]	13384	1			T74	93		T83	323		T84	1
auto[1]	auto[0]	auto[1]	61684	1			T74	487		T83	1617		T153	900
auto[1]	auto[0]	auto[2]	61345	1			T74	506		T83	1583		T153	982
auto[1]	auto[0]	auto[3]	275903	1			T97	2		T63	1		T74	2308
auto[1]	auto[1]	auto[0]	3446983	1			T7	107101		T59	77704		T74	194
auto[1]	auto[1]	auto[1]	632382	1			T7	10520		T59	7932		T74	1524
auto[1]	auto[1]	auto[2]	605994	1			T7	10800		T59	7808		T45	1
auto[1]	auto[1]	auto[3]	1402261	1			T7	1033		T59	765		T74	6780
auto[1]	auto[2]	auto[0]	9935	1			T83	204		T154	254		T155	290
auto[1]	auto[2]	auto[1]	44655	1			T83	939		T154	994		T155	1277
auto[1]	auto[2]	auto[2]	50745	1			T74	468		T83	1541		T153	824
auto[1]	auto[2]	auto[3]	227105	1			T74	2112		T83	6668		T153	3866
auto[1]	auto[3]	auto[0]	3442981	1			T7	106615		T59	78203		T45	1
auto[1]	auto[3]	auto[1]	590841	1			T7	10787		T59	7993		T74	393
auto[1]	auto[3]	auto[2]	620920	1			T7	10751		T59	7991		T74	1446
auto[1]	auto[3]	auto[3]	1356495	1			T7	1024		T59	813		T74	6516