Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1162729303	202000	0	0
ctrl_regwen_rd_A	1162729303	5786	0	0
exec_rd_A	1162729303	5358	0	0
exec_regwen_rd_A	1162729303	5577	0	0
readback_rd_A	1162729303	3622	0	0
readback_regwen_rd_A	1162729303	3395	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	202000	0	0
T8	101637	0	0	0
T9	160110	0	0	0
T25	169911	0	0	0
T26	54049	2392	0	0
T29	0	2519	0	0
T30	0	3397	0	0
T48	243102	0	0	0
T57	0	4063	0	0
T76	0	4905	0	0
T77	0	2217	0	0
T78	0	962	0	0
T79	0	5913	0	0
T80	0	5901	0	0
T81	0	2375	0	0
T82	77375	0	0	0
T83	136925	0	0	0
T84	265377	0	0	0
T85	73676	0	0	0
T86	66331	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	5786	0	0
T49	0	604	0	0
T76	107426	382	0	0
T80	0	388	0	0
T119	0	97	0	0
T120	0	222	0	0
T121	0	147	0	0
T122	0	103	0	0
T123	0	320	0	0
T124	0	40	0	0
T125	0	105	0	0
T126	323436	0	0	0
T127	128574	0	0	0
T128	552122	0	0	0
T129	386967	0	0	0
T130	40609	0	0	0
T131	106280	0	0	0
T132	148373	0	0	0
T133	70824	0	0	0
T134	144801	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	5358	0	0
T49	0	729	0	0
T76	107426	364	0	0
T80	0	470	0	0
T119	0	70	0	0
T120	0	127	0	0
T121	0	101	0	0
T122	0	112	0	0
T123	0	243	0	0
T124	0	39	0	0
T125	0	121	0	0
T126	323436	0	0	0
T127	128574	0	0	0
T128	552122	0	0	0
T129	386967	0	0	0
T130	40609	0	0	0
T131	106280	0	0	0
T132	148373	0	0	0
T133	70824	0	0	0
T134	144801	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	5577	0	0
T49	0	677	0	0
T76	107426	368	0	0
T80	0	411	0	0
T119	0	96	0	0
T120	0	203	0	0
T121	0	104	0	0
T122	0	106	0	0
T123	0	226	0	0
T124	0	37	0	0
T125	0	104	0	0
T126	323436	0	0	0
T127	128574	0	0	0
T128	552122	0	0	0
T129	386967	0	0	0
T130	40609	0	0	0
T131	106280	0	0	0
T132	148373	0	0	0
T133	70824	0	0	0
T134	144801	0	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	3622	0	0
T49	0	598	0	0
T76	107426	332	0	0
T80	0	308	0	0
T119	0	96	0	0
T120	0	139	0	0
T121	0	97	0	0
T122	0	41	0	0
T123	0	204	0	0
T124	0	48	0	0
T125	0	73	0	0
T126	323436	0	0	0
T127	128574	0	0	0
T128	552122	0	0	0
T129	386967	0	0	0
T130	40609	0	0	0
T131	106280	0	0	0
T132	148373	0	0	0
T133	70824	0	0	0
T134	144801	0	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1162729303	3395	0	0
T49	0	574	0	0
T76	107426	277	0	0
T80	0	417	0	0
T119	0	62	0	0
T120	0	185	0	0
T121	0	100	0	0
T122	0	70	0	0
T123	0	204	0	0
T124	0	49	0	0
T125	0	60	0	0
T126	323436	0	0	0
T127	128574	0	0	0
T128	552122	0	0	0
T129	386967	0	0	0
T130	40609	0	0	0
T131	106280	0	0	0
T132	148373	0	0	0
T133	70824	0	0	0
T134	144801	0	0	0