Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	16	0	16	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csr_exec_cp	3	0	3	100.00	100	1	1	0
en_sram_ifetch_cp	3	0	3	100.00	100	1	1	0
lc_hw_debug_en_cp	3	0	3	100.00	100	1	1	0

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::executable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
executable_cross	16	0	16	100.00	100	1	1	0

Summary for Variable csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csr_exec_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
instr_invalid_dis	375068816	1			T1	20000		T2	393212		T4	130638
instr_valid_dis	321325268	1			T1	20000		T2	393212		T4	130638
instr_en	45368978	1			T6	96078		T14	299580		T20	167446

---

Summary for Variable en_sram_ifetch_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for en_sram_ifetch_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sram_ifetch_invalid_disable	17757246	1			T6	47574		T14	295429		T20	162056
sram_ifetch_valid_disable	322375172	1			T1	20000		T2	393212		T4	130638
sram_ifetch_enable	34936398	1			T6	276658		T14	775428		T20	104724

---

Summary for Variable lc_hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for lc_hw_debug_en_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	375068816	1			T1	20000		T2	393212		T4	130638
hw_debug_en_valid_off	324448930	1			T1	20000		T2	393212		T4	130638
hw_debug_en_on	37641644	1			T6	118172		T14	798028		T20	169122

---

Summary for Cross executable_cross

Samples crossed: lc_hw_debug_en_cp en_sram_ifetch_cp csr_exec_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	16	0	16	100.00
Automatically Generated Cross Bins	12	0	12	100.00
User Defined Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for executable_cross

Bins

lc_hw_debug_en_cp	en_sram_ifetch_cp	csr_exec_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_invalid_dis	322375172	1			T1	20000		T2	393212		T4	130638
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_valid_dis	303260534	1			T1	20000		T2	393212		T4	130638
hw_debug_en_invalid_off	sram_ifetch_valid_disable	instr_en	15776710	1			T6	38148		T14	62534		T20	87724
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_invalid_dis	7224902	1			T6	46968		T14	291503		T20	104802
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_valid_dis	1667072	1			T6	46968		T14	87964		T20	55282
hw_debug_en_valid_off	sram_ifetch_invalid_disable	instr_en	4787636	1			T14	280048		T20	49520		T141	10550
hw_debug_en_on	sram_ifetch_invalid_disable	instr_invalid_dis	6148546	1			T6	606		T20	57254		T15	20000
hw_debug_en_on	sram_ifetch_invalid_disable	instr_valid_dis	1887684	1			T6	606		T20	57254		T70	3174
hw_debug_en_on	sram_ifetch_invalid_disable	instr_en	3371460	1			T15	20000		T141	46466		T145	30428
hw_debug_en_on	sram_ifetch_valid_disable	instr_invalid_dis	10464886	1			T6	79516		T14	202374		T20	81666
hw_debug_en_on	sram_ifetch_valid_disable	instr_valid_dis	3759288	1			T6	50452		T14	78030		T20	81666
hw_debug_en_on	sram_ifetch_valid_disable	instr_en	5043740	1			T14	41168		T145	132158		T147	104384

User Defined Cross Bins for executable_cross

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
csr_exec_en	20229938	1			T6	57930		T14	112524		T20	30202
lc_exec_en	21028212	1			T6	38050		T14	595654		T20	30202
valid_exec_dis	319272236	1			T1	20000		T2	393212		T4	130638
invalid_exec_dis	52693644	1			T6	324232		T14	372972		T20	266780