Unified Coverage Report :: Group :: sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

Group : sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sram_ctrl_env_0.1/sram_ctrl_env_cov.sv

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Summary for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	10	0	10	100.00

Variables for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
subword_granularity_cp	5	0	5	100.00	100	1	1	0
subword_we_cp	2	0	2	100.00	100	1	1	2

Crosses for Group sram_ctrl_env_pkg::sram_ctrl_env_cov#(15)::subword_access_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
subword_access	10	0	10	100.00	100	1	1	0

Summary for Variable subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for subword_granularity_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
ill_access	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
word_access	156959328	1			T1	10000		T2	196606		T4	3247
triple_byte_access	2851467	1			T4	7435		T5	129		T6	2648
halfword_access	4380687	1			T4	13864		T5	178		T6	4019
byte_access	6138177	1			T4	25693		T5	230		T6	5377
zero_access	1872677	1			T4	15080		T5	58		T6	1358

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Summary for Variable subword_we_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for subword_we_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

86124981

1

T1

5064

T2

65536

T4

32495

auto[1]

86077355

1

T1

4936

T2

131070

T4

32824

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Summary for Cross subword_access

Samples crossed: subword_we_cp subword_granularity_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for subword_access

Bins

subword_we_cp	subword_granularity_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	word_access	78343086	1			T1	5064		T2	65536		T4	269
auto[0]	triple_byte_access	1359966	1			T4	1450		T5	71		T6	1472
auto[0]	halfword_access	2141816	1			T4	4794		T5	86		T6	2156
auto[0]	byte_access	3153263	1			T4	13894		T5	111		T6	2882
auto[0]	zero_access	1126850	1			T4	12088		T5	36		T6	754
auto[1]	word_access	78616242	1			T1	4936		T2	131070		T4	2978
auto[1]	triple_byte_access	1491501	1			T4	5985		T5	58		T6	1176
auto[1]	halfword_access	2238871	1			T4	9070		T5	92		T6	1863
auto[1]	byte_access	2984914	1			T4	11799		T5	119		T6	2495
auto[1]	zero_access	745827	1			T4	2992		T5	22		T6	604