| T797 |
/workspace/coverage/default/10.sram_ctrl_smoke.4048744561 |
|
|
Aug 07 07:03:39 PM PDT 24 |
Aug 07 07:04:01 PM PDT 24 |
908928981 ps |
| T798 |
/workspace/coverage/default/0.sram_ctrl_partial_access.734089211 |
|
|
Aug 07 07:02:58 PM PDT 24 |
Aug 07 07:03:21 PM PDT 24 |
2127984382 ps |
| T799 |
/workspace/coverage/default/2.sram_ctrl_partial_access.166880183 |
|
|
Aug 07 07:03:09 PM PDT 24 |
Aug 07 07:03:15 PM PDT 24 |
1396007992 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_partial_access.4137308169 |
|
|
Aug 07 07:07:23 PM PDT 24 |
Aug 07 07:08:23 PM PDT 24 |
3189822358 ps |
| T801 |
/workspace/coverage/default/28.sram_ctrl_lc_escalation.2586256644 |
|
|
Aug 07 07:07:41 PM PDT 24 |
Aug 07 07:07:49 PM PDT 24 |
1087963051 ps |
| T802 |
/workspace/coverage/default/7.sram_ctrl_bijection.2948244100 |
|
|
Aug 07 07:03:25 PM PDT 24 |
Aug 07 07:23:45 PM PDT 24 |
101609861502 ps |
| T803 |
/workspace/coverage/default/7.sram_ctrl_smoke.1020900338 |
|
|
Aug 07 07:03:24 PM PDT 24 |
Aug 07 07:03:45 PM PDT 24 |
1338331159 ps |
| T804 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.3006961700 |
|
|
Aug 07 07:09:00 PM PDT 24 |
Aug 07 07:09:30 PM PDT 24 |
15887130425 ps |
| T805 |
/workspace/coverage/default/14.sram_ctrl_smoke.1493587499 |
|
|
Aug 07 07:04:26 PM PDT 24 |
Aug 07 07:04:44 PM PDT 24 |
3749283100 ps |
| T806 |
/workspace/coverage/default/37.sram_ctrl_mem_walk.1433870402 |
|
|
Aug 07 07:09:25 PM PDT 24 |
Aug 07 07:11:34 PM PDT 24 |
2082111909 ps |
| T807 |
/workspace/coverage/default/46.sram_ctrl_alert_test.2023166173 |
|
|
Aug 07 07:11:14 PM PDT 24 |
Aug 07 07:11:15 PM PDT 24 |
12938302 ps |
| T808 |
/workspace/coverage/default/13.sram_ctrl_partial_access.2501399036 |
|
|
Aug 07 07:04:18 PM PDT 24 |
Aug 07 07:05:31 PM PDT 24 |
813979568 ps |
| T809 |
/workspace/coverage/default/7.sram_ctrl_multiple_keys.3667082759 |
|
|
Aug 07 07:03:24 PM PDT 24 |
Aug 07 07:15:01 PM PDT 24 |
5812297341 ps |
| T810 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1557488595 |
|
|
Aug 07 07:04:04 PM PDT 24 |
Aug 07 07:04:33 PM PDT 24 |
2850736758 ps |
| T811 |
/workspace/coverage/default/49.sram_ctrl_max_throughput.4151299175 |
|
|
Aug 07 07:11:44 PM PDT 24 |
Aug 07 07:11:51 PM PDT 24 |
689217161 ps |
| T812 |
/workspace/coverage/default/8.sram_ctrl_executable.2383386296 |
|
|
Aug 07 07:03:33 PM PDT 24 |
Aug 07 07:25:24 PM PDT 24 |
9660960921 ps |
| T813 |
/workspace/coverage/default/35.sram_ctrl_mem_partial_access.358572558 |
|
|
Aug 07 07:08:58 PM PDT 24 |
Aug 07 07:11:30 PM PDT 24 |
2496508871 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.274699611 |
|
|
Aug 07 07:03:06 PM PDT 24 |
Aug 07 07:17:05 PM PDT 24 |
45524198472 ps |
| T815 |
/workspace/coverage/default/35.sram_ctrl_bijection.4235276695 |
|
|
Aug 07 07:08:52 PM PDT 24 |
Aug 07 07:39:16 PM PDT 24 |
783037322953 ps |
| T816 |
/workspace/coverage/default/24.sram_ctrl_partial_access.1190588951 |
|
|
Aug 07 07:06:37 PM PDT 24 |
Aug 07 07:08:36 PM PDT 24 |
1926882665 ps |
| T817 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.2447838476 |
|
|
Aug 07 07:10:24 PM PDT 24 |
Aug 07 07:12:59 PM PDT 24 |
12225698887 ps |
| T818 |
/workspace/coverage/default/0.sram_ctrl_bijection.3722312424 |
|
|
Aug 07 07:03:00 PM PDT 24 |
Aug 07 07:36:10 PM PDT 24 |
345500625556 ps |
| T819 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.1229514857 |
|
|
Aug 07 07:04:48 PM PDT 24 |
Aug 07 07:05:33 PM PDT 24 |
759471138 ps |
| T820 |
/workspace/coverage/default/49.sram_ctrl_stress_all.694410166 |
|
|
Aug 07 07:11:52 PM PDT 24 |
Aug 07 08:11:39 PM PDT 24 |
305744549149 ps |
| T821 |
/workspace/coverage/default/39.sram_ctrl_partial_access_b2b.2324486535 |
|
|
Aug 07 07:09:44 PM PDT 24 |
Aug 07 07:14:44 PM PDT 24 |
10090859507 ps |
| T822 |
/workspace/coverage/default/19.sram_ctrl_access_during_key_req.4132687908 |
|
|
Aug 07 07:05:32 PM PDT 24 |
Aug 07 07:11:42 PM PDT 24 |
6744177814 ps |
| T823 |
/workspace/coverage/default/8.sram_ctrl_max_throughput.252929830 |
|
|
Aug 07 07:03:29 PM PDT 24 |
Aug 07 07:03:37 PM PDT 24 |
2694825964 ps |
| T824 |
/workspace/coverage/default/17.sram_ctrl_stress_all.1349616676 |
|
|
Aug 07 07:05:13 PM PDT 24 |
Aug 07 08:36:34 PM PDT 24 |
82990759471 ps |
| T825 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.997580520 |
|
|
Aug 07 07:03:17 PM PDT 24 |
Aug 07 07:18:25 PM PDT 24 |
7652304821 ps |
| T826 |
/workspace/coverage/default/13.sram_ctrl_mem_walk.2329288117 |
|
|
Aug 07 07:04:26 PM PDT 24 |
Aug 07 07:10:02 PM PDT 24 |
76706049518 ps |
| T827 |
/workspace/coverage/default/9.sram_ctrl_regwen.3357595538 |
|
|
Aug 07 07:03:40 PM PDT 24 |
Aug 07 07:19:37 PM PDT 24 |
26335714360 ps |
| T828 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.3756911190 |
|
|
Aug 07 07:03:17 PM PDT 24 |
Aug 07 07:03:46 PM PDT 24 |
3745803325 ps |
| T829 |
/workspace/coverage/default/35.sram_ctrl_partial_access_b2b.191375003 |
|
|
Aug 07 07:08:52 PM PDT 24 |
Aug 07 07:14:27 PM PDT 24 |
13770896427 ps |
| T830 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.2988305271 |
|
|
Aug 07 07:08:21 PM PDT 24 |
Aug 07 07:09:43 PM PDT 24 |
24453109250 ps |
| T831 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1301683057 |
|
|
Aug 07 07:04:47 PM PDT 24 |
Aug 07 07:04:48 PM PDT 24 |
15747569 ps |
| T832 |
/workspace/coverage/default/31.sram_ctrl_regwen.2833172404 |
|
|
Aug 07 07:08:17 PM PDT 24 |
Aug 07 07:24:01 PM PDT 24 |
10172989572 ps |
| T833 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.1103552318 |
|
|
Aug 07 07:07:48 PM PDT 24 |
Aug 07 07:07:51 PM PDT 24 |
357824877 ps |
| T834 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.1362555902 |
|
|
Aug 07 07:11:07 PM PDT 24 |
Aug 07 07:21:13 PM PDT 24 |
15055660815 ps |
| T835 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.1241643727 |
|
|
Aug 07 07:06:16 PM PDT 24 |
Aug 07 07:10:42 PM PDT 24 |
18255203041 ps |
| T836 |
/workspace/coverage/default/39.sram_ctrl_mem_partial_access.2331034014 |
|
|
Aug 07 07:09:46 PM PDT 24 |
Aug 07 07:12:17 PM PDT 24 |
34645651852 ps |
| T837 |
/workspace/coverage/default/31.sram_ctrl_alert_test.3702667413 |
|
|
Aug 07 07:08:16 PM PDT 24 |
Aug 07 07:08:17 PM PDT 24 |
17439210 ps |
| T838 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1280857686 |
|
|
Aug 07 07:06:18 PM PDT 24 |
Aug 07 07:11:29 PM PDT 24 |
17224354275 ps |
| T839 |
/workspace/coverage/default/45.sram_ctrl_bijection.904022548 |
|
|
Aug 07 07:10:52 PM PDT 24 |
Aug 07 07:53:48 PM PDT 24 |
156524512942 ps |
| T840 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3283462390 |
|
|
Aug 07 07:08:20 PM PDT 24 |
Aug 07 07:08:42 PM PDT 24 |
1403633862 ps |
| T841 |
/workspace/coverage/default/33.sram_ctrl_throughput_w_partial_write.1216480239 |
|
|
Aug 07 07:08:37 PM PDT 24 |
Aug 07 07:09:49 PM PDT 24 |
12508451612 ps |
| T842 |
/workspace/coverage/default/38.sram_ctrl_stress_all.2279499412 |
|
|
Aug 07 07:09:37 PM PDT 24 |
Aug 07 09:19:18 PM PDT 24 |
1022576383455 ps |
| T843 |
/workspace/coverage/default/30.sram_ctrl_lc_escalation.416084787 |
|
|
Aug 07 07:08:00 PM PDT 24 |
Aug 07 07:08:37 PM PDT 24 |
5184606953 ps |
| T844 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.4262028142 |
|
|
Aug 07 07:09:55 PM PDT 24 |
Aug 07 07:09:58 PM PDT 24 |
707231836 ps |
| T845 |
/workspace/coverage/default/0.sram_ctrl_mem_partial_access.3252302786 |
|
|
Aug 07 07:03:09 PM PDT 24 |
Aug 07 07:05:13 PM PDT 24 |
6117956885 ps |
| T846 |
/workspace/coverage/default/42.sram_ctrl_alert_test.1035772137 |
|
|
Aug 07 07:10:25 PM PDT 24 |
Aug 07 07:10:26 PM PDT 24 |
13894560 ps |
| T847 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.3758009510 |
|
|
Aug 07 07:06:51 PM PDT 24 |
Aug 07 07:09:32 PM PDT 24 |
19968868378 ps |
| T848 |
/workspace/coverage/default/21.sram_ctrl_ram_cfg.1061796678 |
|
|
Aug 07 07:06:09 PM PDT 24 |
Aug 07 07:06:13 PM PDT 24 |
347192491 ps |
| T849 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.3370321803 |
|
|
Aug 07 07:03:47 PM PDT 24 |
Aug 07 07:04:00 PM PDT 24 |
704333820 ps |
| T850 |
/workspace/coverage/default/29.sram_ctrl_bijection.2204836930 |
|
|
Aug 07 07:07:50 PM PDT 24 |
Aug 07 07:53:48 PM PDT 24 |
288519023636 ps |
| T851 |
/workspace/coverage/default/48.sram_ctrl_regwen.1342115016 |
|
|
Aug 07 07:11:36 PM PDT 24 |
Aug 07 07:15:02 PM PDT 24 |
23795643567 ps |
| T852 |
/workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.1324552467 |
|
|
Aug 07 07:03:16 PM PDT 24 |
Aug 07 07:05:41 PM PDT 24 |
4592293089 ps |
| T853 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.1472801692 |
|
|
Aug 07 07:11:37 PM PDT 24 |
Aug 07 07:11:40 PM PDT 24 |
1349330097 ps |
| T854 |
/workspace/coverage/default/35.sram_ctrl_multiple_keys.4065957296 |
|
|
Aug 07 07:08:52 PM PDT 24 |
Aug 07 07:29:25 PM PDT 24 |
11867039795 ps |
| T855 |
/workspace/coverage/default/4.sram_ctrl_bijection.1587430660 |
|
|
Aug 07 07:03:15 PM PDT 24 |
Aug 07 07:23:40 PM PDT 24 |
55426771137 ps |
| T856 |
/workspace/coverage/default/9.sram_ctrl_alert_test.3782488905 |
|
|
Aug 07 07:03:44 PM PDT 24 |
Aug 07 07:03:44 PM PDT 24 |
28419593 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.2337399041 |
|
|
Aug 07 07:10:06 PM PDT 24 |
Aug 07 07:19:30 PM PDT 24 |
5635986023 ps |
| T858 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.3927807607 |
|
|
Aug 07 07:06:28 PM PDT 24 |
Aug 07 07:06:31 PM PDT 24 |
347148533 ps |
| T859 |
/workspace/coverage/default/27.sram_ctrl_alert_test.2958609314 |
|
|
Aug 07 07:07:32 PM PDT 24 |
Aug 07 07:07:33 PM PDT 24 |
15199162 ps |
| T860 |
/workspace/coverage/default/8.sram_ctrl_alert_test.251999036 |
|
|
Aug 07 07:03:36 PM PDT 24 |
Aug 07 07:03:37 PM PDT 24 |
20291049 ps |
| T861 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1203440083 |
|
|
Aug 07 07:09:09 PM PDT 24 |
Aug 07 07:28:34 PM PDT 24 |
68766511142 ps |
| T862 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1987991729 |
|
|
Aug 07 07:08:15 PM PDT 24 |
Aug 07 08:21:07 PM PDT 24 |
90694403015 ps |
| T863 |
/workspace/coverage/default/23.sram_ctrl_smoke.2003915440 |
|
|
Aug 07 07:06:22 PM PDT 24 |
Aug 07 07:06:32 PM PDT 24 |
2099735904 ps |
| T864 |
/workspace/coverage/default/35.sram_ctrl_executable.1849839049 |
|
|
Aug 07 07:08:58 PM PDT 24 |
Aug 07 07:41:20 PM PDT 24 |
221313794603 ps |
| T865 |
/workspace/coverage/default/21.sram_ctrl_partial_access.1682436164 |
|
|
Aug 07 07:06:04 PM PDT 24 |
Aug 07 07:06:12 PM PDT 24 |
1547215129 ps |
| T866 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.3758172182 |
|
|
Aug 07 07:09:16 PM PDT 24 |
Aug 07 07:14:26 PM PDT 24 |
5529224127 ps |
| T867 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.2186500781 |
|
|
Aug 07 07:10:36 PM PDT 24 |
Aug 07 07:23:24 PM PDT 24 |
14205698962 ps |
| T868 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3547298179 |
|
|
Aug 07 07:11:37 PM PDT 24 |
Aug 07 07:11:38 PM PDT 24 |
21530020 ps |
| T869 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.1732618374 |
|
|
Aug 07 07:07:06 PM PDT 24 |
Aug 07 07:29:14 PM PDT 24 |
69789720936 ps |
| T870 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.1000705626 |
|
|
Aug 07 07:11:27 PM PDT 24 |
Aug 07 07:25:08 PM PDT 24 |
21004770032 ps |
| T871 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.4109868013 |
|
|
Aug 07 07:10:00 PM PDT 24 |
Aug 07 07:14:06 PM PDT 24 |
8697127006 ps |
| T872 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.1518063421 |
|
|
Aug 07 07:08:08 PM PDT 24 |
Aug 07 07:11:24 PM PDT 24 |
12023305647 ps |
| T873 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.3325126711 |
|
|
Aug 07 07:09:53 PM PDT 24 |
Aug 07 07:19:34 PM PDT 24 |
21979623678 ps |
| T874 |
/workspace/coverage/default/27.sram_ctrl_smoke.182975199 |
|
|
Aug 07 07:07:17 PM PDT 24 |
Aug 07 07:07:32 PM PDT 24 |
2886630958 ps |
| T875 |
/workspace/coverage/default/36.sram_ctrl_throughput_w_partial_write.3124815092 |
|
|
Aug 07 07:09:07 PM PDT 24 |
Aug 07 07:09:24 PM PDT 24 |
719853964 ps |
| T876 |
/workspace/coverage/default/6.sram_ctrl_lc_escalation.2462538099 |
|
|
Aug 07 07:03:27 PM PDT 24 |
Aug 07 07:04:21 PM PDT 24 |
36338068025 ps |
| T877 |
/workspace/coverage/default/30.sram_ctrl_stress_all.4244023798 |
|
|
Aug 07 07:08:09 PM PDT 24 |
Aug 07 08:52:40 PM PDT 24 |
160696258410 ps |
| T878 |
/workspace/coverage/default/17.sram_ctrl_throughput_w_partial_write.296329591 |
|
|
Aug 07 07:05:06 PM PDT 24 |
Aug 07 07:05:21 PM PDT 24 |
2920674431 ps |
| T879 |
/workspace/coverage/default/48.sram_ctrl_executable.1080313330 |
|
|
Aug 07 07:11:37 PM PDT 24 |
Aug 07 07:37:39 PM PDT 24 |
24958473937 ps |
| T880 |
/workspace/coverage/default/27.sram_ctrl_executable.4241643897 |
|
|
Aug 07 07:07:24 PM PDT 24 |
Aug 07 07:24:31 PM PDT 24 |
31789986966 ps |
| T881 |
/workspace/coverage/default/3.sram_ctrl_max_throughput.1871208183 |
|
|
Aug 07 07:03:16 PM PDT 24 |
Aug 07 07:03:30 PM PDT 24 |
698747968 ps |
| T882 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3162286163 |
|
|
Aug 07 07:03:07 PM PDT 24 |
Aug 07 07:06:06 PM PDT 24 |
808685576 ps |
| T883 |
/workspace/coverage/default/16.sram_ctrl_multiple_keys.1697152715 |
|
|
Aug 07 07:04:44 PM PDT 24 |
Aug 07 07:19:08 PM PDT 24 |
40532982020 ps |
| T884 |
/workspace/coverage/default/23.sram_ctrl_regwen.1903916242 |
|
|
Aug 07 07:06:30 PM PDT 24 |
Aug 07 07:17:35 PM PDT 24 |
2821218678 ps |
| T885 |
/workspace/coverage/default/13.sram_ctrl_stress_pipeline.3407302781 |
|
|
Aug 07 07:04:18 PM PDT 24 |
Aug 07 07:08:12 PM PDT 24 |
93394605525 ps |
| T886 |
/workspace/coverage/default/15.sram_ctrl_mem_partial_access.920797231 |
|
|
Aug 07 07:04:36 PM PDT 24 |
Aug 07 07:07:05 PM PDT 24 |
8442391612 ps |
| T887 |
/workspace/coverage/default/17.sram_ctrl_alert_test.1205796582 |
|
|
Aug 07 07:05:13 PM PDT 24 |
Aug 07 07:05:14 PM PDT 24 |
40501790 ps |
| T888 |
/workspace/coverage/default/15.sram_ctrl_mem_walk.2937739566 |
|
|
Aug 07 07:04:39 PM PDT 24 |
Aug 07 07:07:24 PM PDT 24 |
7211667116 ps |
| T889 |
/workspace/coverage/default/32.sram_ctrl_mem_partial_access.2961624683 |
|
|
Aug 07 07:08:35 PM PDT 24 |
Aug 07 07:09:57 PM PDT 24 |
2438353227 ps |
| T890 |
/workspace/coverage/default/42.sram_ctrl_regwen.3104593945 |
|
|
Aug 07 07:10:23 PM PDT 24 |
Aug 07 07:32:21 PM PDT 24 |
59152467674 ps |
| T891 |
/workspace/coverage/default/12.sram_ctrl_executable.2825150407 |
|
|
Aug 07 07:04:18 PM PDT 24 |
Aug 07 07:14:42 PM PDT 24 |
6222132061 ps |
| T892 |
/workspace/coverage/default/7.sram_ctrl_mem_partial_access.1005984489 |
|
|
Aug 07 07:03:31 PM PDT 24 |
Aug 07 07:05:48 PM PDT 24 |
24306848456 ps |
| T893 |
/workspace/coverage/default/4.sram_ctrl_partial_access.703667287 |
|
|
Aug 07 07:03:15 PM PDT 24 |
Aug 07 07:03:40 PM PDT 24 |
1723224087 ps |
| T894 |
/workspace/coverage/default/28.sram_ctrl_throughput_w_partial_write.4120680109 |
|
|
Aug 07 07:07:46 PM PDT 24 |
Aug 07 07:10:12 PM PDT 24 |
1030792340 ps |
| T895 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.167514277 |
|
|
Aug 07 07:07:31 PM PDT 24 |
Aug 07 07:08:08 PM PDT 24 |
5942759928 ps |
| T896 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.3919555432 |
|
|
Aug 07 07:08:43 PM PDT 24 |
Aug 07 07:14:00 PM PDT 24 |
5616968882 ps |
| T897 |
/workspace/coverage/default/41.sram_ctrl_max_throughput.1893540984 |
|
|
Aug 07 07:10:00 PM PDT 24 |
Aug 07 07:10:50 PM PDT 24 |
3170526039 ps |
| T898 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.1176342380 |
|
|
Aug 07 07:03:48 PM PDT 24 |
Aug 07 07:10:41 PM PDT 24 |
26092718890 ps |
| T899 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1556833127 |
|
|
Aug 07 07:05:00 PM PDT 24 |
Aug 07 08:47:14 PM PDT 24 |
935732161009 ps |
| T900 |
/workspace/coverage/default/40.sram_ctrl_partial_access.2670480776 |
|
|
Aug 07 07:09:54 PM PDT 24 |
Aug 07 07:10:01 PM PDT 24 |
1751161707 ps |
| T901 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3671009896 |
|
|
Aug 07 07:08:59 PM PDT 24 |
Aug 07 08:17:45 PM PDT 24 |
56303358756 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.1105445944 |
|
|
Aug 07 07:03:16 PM PDT 24 |
Aug 07 07:05:50 PM PDT 24 |
3512805918 ps |
| T903 |
/workspace/coverage/default/29.sram_ctrl_access_during_key_req.2218354462 |
|
|
Aug 07 07:07:48 PM PDT 24 |
Aug 07 07:24:57 PM PDT 24 |
44045097486 ps |
| T904 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.3914918071 |
|
|
Aug 07 07:11:38 PM PDT 24 |
Aug 07 07:14:28 PM PDT 24 |
7268270318 ps |
| T905 |
/workspace/coverage/default/15.sram_ctrl_lc_escalation.1135962081 |
|
|
Aug 07 07:04:30 PM PDT 24 |
Aug 07 07:05:45 PM PDT 24 |
40237882225 ps |
| T906 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.270064662 |
|
|
Aug 07 07:06:22 PM PDT 24 |
Aug 07 07:13:23 PM PDT 24 |
17182167879 ps |
| T907 |
/workspace/coverage/default/34.sram_ctrl_regwen.2166741708 |
|
|
Aug 07 07:08:44 PM PDT 24 |
Aug 07 07:38:55 PM PDT 24 |
3823338756 ps |
| T908 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1939233432 |
|
|
Aug 07 07:05:17 PM PDT 24 |
Aug 07 07:06:37 PM PDT 24 |
784452785 ps |
| T909 |
/workspace/coverage/default/19.sram_ctrl_executable.3565573247 |
|
|
Aug 07 07:05:31 PM PDT 24 |
Aug 07 07:29:12 PM PDT 24 |
22125594195 ps |
| T910 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1237358702 |
|
|
Aug 07 07:04:26 PM PDT 24 |
Aug 07 07:09:27 PM PDT 24 |
7505093308 ps |
| T911 |
/workspace/coverage/default/22.sram_ctrl_smoke.765133078 |
|
|
Aug 07 07:06:16 PM PDT 24 |
Aug 07 07:06:32 PM PDT 24 |
3295232486 ps |
| T912 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.2991805520 |
|
|
Aug 07 07:07:05 PM PDT 24 |
Aug 07 07:07:32 PM PDT 24 |
6459537045 ps |
| T913 |
/workspace/coverage/default/33.sram_ctrl_alert_test.3522763831 |
|
|
Aug 07 07:08:46 PM PDT 24 |
Aug 07 07:08:47 PM PDT 24 |
32322249 ps |
| T914 |
/workspace/coverage/default/45.sram_ctrl_throughput_w_partial_write.3788109169 |
|
|
Aug 07 07:10:51 PM PDT 24 |
Aug 07 07:11:03 PM PDT 24 |
5704550305 ps |
| T915 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.681116230 |
|
|
Aug 07 07:06:15 PM PDT 24 |
Aug 07 07:06:19 PM PDT 24 |
378579852 ps |
| T916 |
/workspace/coverage/default/16.sram_ctrl_executable.106662046 |
|
|
Aug 07 07:04:53 PM PDT 24 |
Aug 07 07:10:45 PM PDT 24 |
11926448241 ps |
| T917 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.359840380 |
|
|
Aug 07 07:09:45 PM PDT 24 |
Aug 07 07:16:16 PM PDT 24 |
6292158228 ps |
| T918 |
/workspace/coverage/default/47.sram_ctrl_access_during_key_req.4022325510 |
|
|
Aug 07 07:11:16 PM PDT 24 |
Aug 07 07:18:21 PM PDT 24 |
5570771022 ps |
| T919 |
/workspace/coverage/default/5.sram_ctrl_throughput_w_partial_write.2996053257 |
|
|
Aug 07 07:03:23 PM PDT 24 |
Aug 07 07:03:43 PM PDT 24 |
1681187192 ps |
| T920 |
/workspace/coverage/default/40.sram_ctrl_regwen.9503059 |
|
|
Aug 07 07:09:52 PM PDT 24 |
Aug 07 07:33:35 PM PDT 24 |
55335845705 ps |
| T921 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2841338150 |
|
|
Aug 07 07:05:01 PM PDT 24 |
Aug 07 07:05:01 PM PDT 24 |
115791939 ps |
| T922 |
/workspace/coverage/default/46.sram_ctrl_smoke.1781411313 |
|
|
Aug 07 07:11:05 PM PDT 24 |
Aug 07 07:12:58 PM PDT 24 |
901540008 ps |
| T923 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.2409889986 |
|
|
Aug 07 07:04:54 PM PDT 24 |
Aug 07 07:05:47 PM PDT 24 |
8614563117 ps |
| T924 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1994951991 |
|
|
Aug 07 07:08:17 PM PDT 24 |
Aug 07 07:08:20 PM PDT 24 |
1409235071 ps |
| T925 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1707517288 |
|
|
Aug 07 07:04:23 PM PDT 24 |
Aug 07 07:04:27 PM PDT 24 |
4781867395 ps |
| T926 |
/workspace/coverage/default/12.sram_ctrl_regwen.1705137737 |
|
|
Aug 07 07:04:17 PM PDT 24 |
Aug 07 07:18:54 PM PDT 24 |
7696418050 ps |
| T927 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.1656824179 |
|
|
Aug 07 07:05:32 PM PDT 24 |
Aug 07 07:08:08 PM PDT 24 |
3471177540 ps |
| T928 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3518577469 |
|
|
Aug 07 07:05:25 PM PDT 24 |
Aug 07 07:08:29 PM PDT 24 |
20061591053 ps |
| T929 |
/workspace/coverage/default/20.sram_ctrl_smoke.3653491245 |
|
|
Aug 07 07:05:38 PM PDT 24 |
Aug 07 07:05:45 PM PDT 24 |
1029824688 ps |
| T930 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.4065975038 |
|
|
Aug 07 07:09:47 PM PDT 24 |
Aug 07 07:09:50 PM PDT 24 |
1263134792 ps |
| T931 |
/workspace/coverage/default/18.sram_ctrl_bijection.3866028004 |
|
|
Aug 07 07:05:13 PM PDT 24 |
Aug 07 07:41:50 PM PDT 24 |
368146405780 ps |
| T932 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.3215327820 |
|
|
Aug 07 07:09:54 PM PDT 24 |
Aug 07 07:10:07 PM PDT 24 |
2035992427 ps |
| T933 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.2614650696 |
|
|
Aug 07 07:04:17 PM PDT 24 |
Aug 07 07:11:48 PM PDT 24 |
96220788420 ps |
| T934 |
/workspace/coverage/default/12.sram_ctrl_partial_access_b2b.2622566065 |
|
|
Aug 07 07:04:03 PM PDT 24 |
Aug 07 07:09:07 PM PDT 24 |
27782326453 ps |
| T935 |
/workspace/coverage/default/39.sram_ctrl_stress_all.3360256458 |
|
|
Aug 07 07:09:47 PM PDT 24 |
Aug 07 08:11:52 PM PDT 24 |
59122638587 ps |
| T936 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.2192397166 |
|
|
Aug 07 07:03:12 PM PDT 24 |
Aug 07 07:09:37 PM PDT 24 |
67253119199 ps |
| T937 |
/workspace/coverage/default/45.sram_ctrl_max_throughput.1236794183 |
|
|
Aug 07 07:10:54 PM PDT 24 |
Aug 07 07:12:27 PM PDT 24 |
820296810 ps |
| T938 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3803599572 |
|
|
Aug 07 07:04:05 PM PDT 24 |
Aug 07 07:04:55 PM PDT 24 |
1527105238 ps |
| T939 |
/workspace/coverage/default/37.sram_ctrl_access_during_key_req.862077243 |
|
|
Aug 07 07:09:23 PM PDT 24 |
Aug 07 07:40:01 PM PDT 24 |
23377911255 ps |
| T940 |
/workspace/coverage/default/13.sram_ctrl_lc_escalation.2669277555 |
|
|
Aug 07 07:04:18 PM PDT 24 |
Aug 07 07:04:36 PM PDT 24 |
10502290995 ps |
| T941 |
/workspace/coverage/default/42.sram_ctrl_multiple_keys.459363751 |
|
|
Aug 07 07:10:15 PM PDT 24 |
Aug 07 07:28:38 PM PDT 24 |
11836358817 ps |
| T942 |
/workspace/coverage/default/43.sram_ctrl_regwen.3694794175 |
|
|
Aug 07 07:10:35 PM PDT 24 |
Aug 07 07:13:12 PM PDT 24 |
1404136085 ps |
| T943 |
/workspace/coverage/default/47.sram_ctrl_smoke.4047020518 |
|
|
Aug 07 07:11:17 PM PDT 24 |
Aug 07 07:13:56 PM PDT 24 |
6784713396 ps |
| T944 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2620818043 |
|
|
Aug 07 07:07:39 PM PDT 24 |
Aug 07 07:12:27 PM PDT 24 |
17797341038 ps |
| T945 |
/workspace/coverage/default/46.sram_ctrl_bijection.2206584356 |
|
|
Aug 07 07:11:05 PM PDT 24 |
Aug 07 07:55:27 PM PDT 24 |
220818846654 ps |
| T946 |
/workspace/coverage/default/22.sram_ctrl_executable.3225812824 |
|
|
Aug 07 07:06:16 PM PDT 24 |
Aug 07 07:12:44 PM PDT 24 |
61361352889 ps |
| T947 |
/workspace/coverage/default/1.sram_ctrl_smoke.3235473096 |
|
|
Aug 07 07:03:06 PM PDT 24 |
Aug 07 07:03:29 PM PDT 24 |
5957760455 ps |
| T67 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3131864166 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:47 PM PDT 24 |
470162196 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.136341606 |
|
|
Aug 07 04:48:28 PM PDT 24 |
Aug 07 04:48:32 PM PDT 24 |
407345825 ps |
| T72 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.4107748225 |
|
|
Aug 07 04:48:56 PM PDT 24 |
Aug 07 04:49:02 PM PDT 24 |
13177262 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.9347522 |
|
|
Aug 07 04:49:00 PM PDT 24 |
Aug 07 04:49:02 PM PDT 24 |
172389315 ps |
| T121 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2298182635 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:48:42 PM PDT 24 |
39568123 ps |
| T68 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.884667088 |
|
|
Aug 07 04:48:46 PM PDT 24 |
Aug 07 04:48:49 PM PDT 24 |
194295774 ps |
| T84 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.1979975479 |
|
|
Aug 07 04:48:36 PM PDT 24 |
Aug 07 04:48:37 PM PDT 24 |
54704085 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4084401143 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:48:44 PM PDT 24 |
386659419 ps |
| T69 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.1143105493 |
|
|
Aug 07 04:48:49 PM PDT 24 |
Aug 07 04:48:52 PM PDT 24 |
944207291 ps |
| T85 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3050114002 |
|
|
Aug 07 04:50:06 PM PDT 24 |
Aug 07 04:50:07 PM PDT 24 |
29512155 ps |
| T950 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.592408448 |
|
|
Aug 07 04:48:45 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
452858249 ps |
| T951 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1367013315 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:49 PM PDT 24 |
1343461932 ps |
| T952 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3031503043 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:45 PM PDT 24 |
174918047 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.342697039 |
|
|
Aug 07 04:48:37 PM PDT 24 |
Aug 07 04:48:38 PM PDT 24 |
97964466 ps |
| T87 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1100824950 |
|
|
Aug 07 04:48:37 PM PDT 24 |
Aug 07 04:48:47 PM PDT 24 |
26651525 ps |
| T88 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3221038128 |
|
|
Aug 07 04:48:49 PM PDT 24 |
Aug 07 04:49:47 PM PDT 24 |
29421029733 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.3191943626 |
|
|
Aug 07 04:49:07 PM PDT 24 |
Aug 07 04:49:36 PM PDT 24 |
5458028695 ps |
| T130 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2281503600 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:45 PM PDT 24 |
305075499 ps |
| T132 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3736810326 |
|
|
Aug 07 04:48:34 PM PDT 24 |
Aug 07 04:48:37 PM PDT 24 |
476683820 ps |
| T112 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.1616397091 |
|
|
Aug 07 04:49:11 PM PDT 24 |
Aug 07 04:49:12 PM PDT 24 |
57057701 ps |
| T122 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2656511376 |
|
|
Aug 07 04:48:38 PM PDT 24 |
Aug 07 04:48:45 PM PDT 24 |
46602613 ps |
| T127 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.112477366 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:44 PM PDT 24 |
220419574 ps |
| T90 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1577763022 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:45 PM PDT 24 |
16938874 ps |
| T953 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3533731699 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
12088213 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2694361785 |
|
|
Aug 07 04:48:28 PM PDT 24 |
Aug 07 04:48:32 PM PDT 24 |
109843431 ps |
| T128 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.2972991820 |
|
|
Aug 07 04:48:50 PM PDT 24 |
Aug 07 04:48:52 PM PDT 24 |
512829435 ps |
| T91 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.3735604025 |
|
|
Aug 07 04:48:48 PM PDT 24 |
Aug 07 04:48:49 PM PDT 24 |
98305266 ps |
| T94 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.2725398699 |
|
|
Aug 07 04:48:34 PM PDT 24 |
Aug 07 04:48:35 PM PDT 24 |
38256269 ps |
| T113 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2065919904 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:42 PM PDT 24 |
190151039 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.1826612177 |
|
|
Aug 07 04:48:36 PM PDT 24 |
Aug 07 04:48:37 PM PDT 24 |
58625101 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.4154403822 |
|
|
Aug 07 04:49:20 PM PDT 24 |
Aug 07 04:49:23 PM PDT 24 |
1594044648 ps |
| T115 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3290700494 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
211663033 ps |
| T116 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2412251326 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:47 PM PDT 24 |
33967171 ps |
| T117 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2368096395 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:48:40 PM PDT 24 |
48581402 ps |
| T95 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2111380653 |
|
|
Aug 07 04:48:32 PM PDT 24 |
Aug 07 04:49:23 PM PDT 24 |
15005135324 ps |
| T105 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3795983855 |
|
|
Aug 07 04:48:39 PM PDT 24 |
Aug 07 04:48:39 PM PDT 24 |
38042856 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.2030164652 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
42931828 ps |
| T957 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2532492546 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
820602235 ps |
| T958 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1710121972 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:48:42 PM PDT 24 |
15703619 ps |
| T959 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.4199064628 |
|
|
Aug 07 04:50:11 PM PDT 24 |
Aug 07 04:50:16 PM PDT 24 |
372115425 ps |
| T96 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1343794907 |
|
|
Aug 07 04:49:13 PM PDT 24 |
Aug 07 04:50:07 PM PDT 24 |
14423249224 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1856080383 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:48:41 PM PDT 24 |
17026883 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1515511210 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
418451529 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.1123161835 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
113083795 ps |
| T963 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.2939017180 |
|
|
Aug 07 04:48:56 PM PDT 24 |
Aug 07 04:48:57 PM PDT 24 |
39659247 ps |
| T97 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.1502041515 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
14372761 ps |
| T964 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4109170911 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
190064711 ps |
| T98 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.266934793 |
|
|
Aug 07 04:48:48 PM PDT 24 |
Aug 07 04:49:14 PM PDT 24 |
3870824987 ps |
| T106 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2685626491 |
|
|
Aug 07 04:48:48 PM PDT 24 |
Aug 07 04:49:44 PM PDT 24 |
7368651704 ps |
| T965 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2292995093 |
|
|
Aug 07 04:49:01 PM PDT 24 |
Aug 07 04:49:01 PM PDT 24 |
48025324 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.2434554788 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
260106741 ps |
| T107 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.4234967318 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:49:10 PM PDT 24 |
3866828232 ps |
| T967 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1182456597 |
|
|
Aug 07 04:48:39 PM PDT 24 |
Aug 07 04:48:40 PM PDT 24 |
303568352 ps |
| T968 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.2163722857 |
|
|
Aug 07 04:48:39 PM PDT 24 |
Aug 07 04:48:40 PM PDT 24 |
16133527 ps |
| T969 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2248794230 |
|
|
Aug 07 04:48:53 PM PDT 24 |
Aug 07 04:48:57 PM PDT 24 |
1229056169 ps |
| T970 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.523121553 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
13512773 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.171893675 |
|
|
Aug 07 04:48:38 PM PDT 24 |
Aug 07 04:49:41 PM PDT 24 |
28198894539 ps |
| T972 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.868381132 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:49:09 PM PDT 24 |
3780815930 ps |
| T131 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1627219673 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
354262555 ps |
| T973 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.230764732 |
|
|
Aug 07 04:48:52 PM PDT 24 |
Aug 07 04:48:56 PM PDT 24 |
2622879938 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3349356583 |
|
|
Aug 07 04:48:35 PM PDT 24 |
Aug 07 04:48:36 PM PDT 24 |
40454247 ps |
| T975 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3854889757 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:48:51 PM PDT 24 |
116034772 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4135191735 |
|
|
Aug 07 04:48:46 PM PDT 24 |
Aug 07 04:48:48 PM PDT 24 |
93766236 ps |
| T977 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.836998834 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
215237456 ps |
| T978 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.608131101 |
|
|
Aug 07 04:49:06 PM PDT 24 |
Aug 07 04:49:10 PM PDT 24 |
1197920978 ps |
| T979 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.1719124331 |
|
|
Aug 07 04:48:43 PM PDT 24 |
Aug 07 04:48:52 PM PDT 24 |
392675077 ps |
| T980 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.799346122 |
|
|
Aug 07 04:48:37 PM PDT 24 |
Aug 07 04:48:38 PM PDT 24 |
59563357 ps |
| T137 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.120042900 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
215784906 ps |
| T108 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.2737101758 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:49:18 PM PDT 24 |
3935733988 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.3193432507 |
|
|
Aug 07 04:48:49 PM PDT 24 |
Aug 07 04:48:50 PM PDT 24 |
43506672 ps |
| T129 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3175437879 |
|
|
Aug 07 04:49:10 PM PDT 24 |
Aug 07 04:49:13 PM PDT 24 |
404014082 ps |
| T982 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.231302138 |
|
|
Aug 07 04:48:33 PM PDT 24 |
Aug 07 04:48:34 PM PDT 24 |
40934005 ps |
| T139 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.824051911 |
|
|
Aug 07 04:49:00 PM PDT 24 |
Aug 07 04:49:02 PM PDT 24 |
642811841 ps |
| T983 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.3961840307 |
|
|
Aug 07 04:49:00 PM PDT 24 |
Aug 07 04:49:04 PM PDT 24 |
1447554773 ps |
| T984 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2210770398 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
1498757527 ps |
| T985 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3271900776 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:49 PM PDT 24 |
575403707 ps |
| T986 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1967892930 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
147399403 ps |
| T987 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.1280953227 |
|
|
Aug 07 04:48:41 PM PDT 24 |
Aug 07 04:48:42 PM PDT 24 |
21182008 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.690998869 |
|
|
Aug 07 04:48:56 PM PDT 24 |
Aug 07 04:48:57 PM PDT 24 |
26780719 ps |
| T989 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3489681862 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
45192028 ps |
| T990 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.96623873 |
|
|
Aug 07 04:48:58 PM PDT 24 |
Aug 07 04:49:02 PM PDT 24 |
364688001 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3410502672 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:48:47 PM PDT 24 |
119714849 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3115891054 |
|
|
Aug 07 04:48:56 PM PDT 24 |
Aug 07 04:48:57 PM PDT 24 |
15522143 ps |
| T993 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.2853843615 |
|
|
Aug 07 04:48:59 PM PDT 24 |
Aug 07 04:49:00 PM PDT 24 |
23050405 ps |
| T994 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2364818959 |
|
|
Aug 07 04:48:31 PM PDT 24 |
Aug 07 04:49:21 PM PDT 24 |
7052604920 ps |
| T995 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.1110854352 |
|
|
Aug 07 04:48:45 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
34451825 ps |
| T996 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1792041387 |
|
|
Aug 07 04:48:47 PM PDT 24 |
Aug 07 04:48:52 PM PDT 24 |
161375117 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.35215949 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:46 PM PDT 24 |
368992124 ps |
| T109 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3216197525 |
|
|
Aug 07 04:48:44 PM PDT 24 |
Aug 07 04:49:16 PM PDT 24 |
20466438314 ps |
| T998 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1392248163 |
|
|
Aug 07 04:48:40 PM PDT 24 |
Aug 07 04:49:30 PM PDT 24 |
7032743081 ps |
| T999 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.861240199 |
|
|
Aug 07 04:48:42 PM PDT 24 |
Aug 07 04:48:43 PM PDT 24 |
27593268 ps |
| T140 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3073616042 |
|
|
Aug 07 04:48:37 PM PDT 24 |
Aug 07 04:48:40 PM PDT 24 |
820741569 ps |
| T1000 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3660737102 |
|
|
Aug 07 04:48:57 PM PDT 24 |
Aug 07 04:49:01 PM PDT 24 |
106173401 ps |
| T110 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1106331968 |
|
|
Aug 07 04:48:37 PM PDT 24 |
Aug 07 04:49:33 PM PDT 24 |
7075189673 ps |
| T1001 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.3206233121 |
|
|
Aug 07 04:48:48 PM PDT 24 |
Aug 07 04:49:36 PM PDT 24 |
14468091339 ps |
| T1002 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.951505848 |
|
|
Aug 07 04:48:52 PM PDT 24 |
Aug 07 04:48:53 PM PDT 24 |
55428629 ps |
| T1003 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.148495238 |
|
|
Aug 07 04:48:50 PM PDT 24 |
Aug 07 04:48:54 PM PDT 24 |
2831612426 ps |
| T1004 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.87523655 |
|
|
Aug 07 04:48:32 PM PDT 24 |
Aug 07 04:48:36 PM PDT 24 |
1464581906 ps |
| T1005 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.3435785008 |
|
|
Aug 07 04:48:48 PM PDT 24 |
Aug 07 04:48:52 PM PDT 24 |
1368026204 ps |