Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16682545	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

150048637

1

T1

73

T2

11414

T3

4614

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82114311	1			T1	243		T2	6253		T3	2536
values[0x0]	40650691	1			T1	64		T2	3011		T3	1244
values[0x1]	43966180	1			T1	124		T2	3323		T3	1336

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8487173	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158244009

1

T1

267

T2

11999

T3

4869

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	554507	1			T2	29		T4	15		T8	23
valid_sources[0x01]	881099	1			T2	20		T4	12		T8	21
valid_sources[0x02]	563504	1			T1	2		T2	30		T4	14
valid_sources[0x03]	572843	1			T1	8		T2	83		T4	18
valid_sources[0x04]	1795575	1			T1	5		T2	40		T4	12
valid_sources[0x05]	949352	1			T2	35		T4	13		T8	19
valid_sources[0x06]	606719	1			T2	77		T4	11		T8	17
valid_sources[0x07]	549098	1			T2	56		T4	13		T8	14
valid_sources[0x08]	537232	1			T2	35		T4	16		T8	33
valid_sources[0x09]	571237	1			T2	42		T4	18		T8	17
valid_sources[0x0a]	556709	1			T2	34		T4	15		T8	16
valid_sources[0x0b]	608455	1			T2	2		T4	18		T8	33
valid_sources[0x0c]	2222555	1			T2	12		T4	17		T8	15
valid_sources[0x0d]	550493	1			T2	89		T4	23		T8	19
valid_sources[0x0e]	537737	1			T2	100		T4	12		T8	30
valid_sources[0x0f]	562230	1			T2	74		T4	18		T8	20
valid_sources[0x10]	754909	1			T1	5		T2	156		T4	16
valid_sources[0x11]	561624	1			T2	46		T4	14		T8	18
valid_sources[0x12]	633248	1			T2	63		T4	16		T8	19
valid_sources[0x13]	635491	1			T2	38		T4	14		T8	20
valid_sources[0x14]	590148	1			T2	18		T4	15		T8	28
valid_sources[0x15]	561794	1			T2	25		T4	12		T8	24
valid_sources[0x16]	626430	1			T2	15		T4	18		T8	21
valid_sources[0x17]	543069	1			T2	103		T4	18		T8	25
valid_sources[0x18]	538905	1			T4	26		T8	26		T12	787
valid_sources[0x19]	742302	1			T2	73		T4	13		T8	20
valid_sources[0x1a]	588916	1			T2	41		T4	21		T8	17
valid_sources[0x1b]	2082685	1			T1	3		T2	78		T4	15
valid_sources[0x1c]	542795	1			T1	5		T2	56		T4	18
valid_sources[0x1d]	609652	1			T1	5		T2	31		T4	17
valid_sources[0x1e]	583921	1			T2	17		T4	9		T8	20
valid_sources[0x1f]	548249	1			T2	53		T4	18		T8	28
valid_sources[0x20]	582476	1			T2	16		T4	22		T8	15
valid_sources[0x21]	554714	1			T1	5		T2	61		T4	13
valid_sources[0x22]	563674	1			T2	75		T4	10		T8	19
valid_sources[0x23]	801140	1			T2	109		T4	23		T8	20
valid_sources[0x24]	555267	1			T2	72		T4	18		T8	19
valid_sources[0x25]	586949	1			T1	3		T2	4		T4	18
valid_sources[0x26]	544444	1			T2	5		T4	14		T8	30
valid_sources[0x27]	538391	1			T2	13		T4	8		T8	22
valid_sources[0x28]	574165	1			T2	34		T4	17		T8	17
valid_sources[0x29]	583533	1			T2	108		T4	16		T8	23
valid_sources[0x2a]	543828	1			T1	3		T2	63		T4	15
valid_sources[0x2b]	565835	1			T2	21		T4	20		T8	23
valid_sources[0x2c]	574355	1			T2	40		T4	12		T8	21
valid_sources[0x2d]	542030	1			T2	42		T4	16		T8	28
valid_sources[0x2e]	601495	1			T2	88		T4	11		T8	44
valid_sources[0x2f]	586907	1			T1	2		T4	13		T8	25
valid_sources[0x30]	714982	1			T1	6		T2	6		T4	10
valid_sources[0x31]	542803	1			T2	31		T4	12		T8	26
valid_sources[0x32]	576730	1			T2	71		T4	21		T8	17
valid_sources[0x33]	553383	1			T1	4		T2	28		T4	19
valid_sources[0x34]	1629049	1			T2	44		T4	16		T8	13
valid_sources[0x35]	586082	1			T2	59		T4	19		T8	11
valid_sources[0x36]	574188	1			T2	5		T4	19		T8	28
valid_sources[0x37]	1544494	1			T1	1		T2	14		T4	22
valid_sources[0x38]	584107	1			T2	24		T4	10		T8	14
valid_sources[0x39]	562435	1			T2	53		T4	13		T8	15
valid_sources[0x3a]	643286	1			T4	11		T8	22		T12	861
valid_sources[0x3b]	567065	1			T1	17		T2	68		T4	22
valid_sources[0x3c]	576311	1			T2	38		T4	13		T8	25
valid_sources[0x3d]	568351	1			T2	55		T4	16		T8	20
valid_sources[0x3e]	579990	1			T2	21		T4	13		T8	30
valid_sources[0x3f]	546320	1			T1	5		T2	92		T4	6
valid_sources[0x40]	570205	1			T2	31		T4	18		T8	16
valid_sources[0x41]	1105270	1			T2	76		T4	19		T8	25
valid_sources[0x42]	597321	1			T1	1		T2	35		T4	15
valid_sources[0x43]	1009527	1			T2	21		T4	14		T8	19
valid_sources[0x44]	615838	1			T1	3		T4	7		T8	30
valid_sources[0x45]	632451	1			T1	1		T2	62		T4	9
valid_sources[0x46]	644773	1			T2	61		T4	11		T8	25
valid_sources[0x47]	1792614	1			T1	7		T2	38		T4	12
valid_sources[0x48]	567530	1			T1	10		T2	115		T4	14
valid_sources[0x49]	552994	1			T2	42		T4	22		T8	17
valid_sources[0x4a]	554188	1			T1	1		T2	70		T4	16
valid_sources[0x4b]	1203501	1			T2	29		T4	19		T8	24
valid_sources[0x4c]	570835	1			T1	4		T2	52		T4	20
valid_sources[0x4d]	535363	1			T2	72		T4	16		T8	17
valid_sources[0x4e]	560825	1			T2	38		T4	16		T8	30
valid_sources[0x4f]	542472	1			T2	21		T4	19		T8	14
valid_sources[0x50]	594652	1			T2	27		T4	22		T8	20
valid_sources[0x51]	568082	1			T2	45		T4	19		T8	18
valid_sources[0x52]	557779	1			T1	1		T2	62		T4	8
valid_sources[0x53]	575884	1			T2	12		T4	16		T8	23
valid_sources[0x54]	639865	1			T2	67		T4	10		T8	24
valid_sources[0x55]	588447	1			T1	1		T2	61		T4	14
valid_sources[0x56]	544584	1			T2	62		T4	20		T8	21
valid_sources[0x57]	552939	1			T2	11		T4	12		T8	16
valid_sources[0x58]	1059613	1			T2	15		T4	16		T8	16
valid_sources[0x59]	581828	1			T2	80		T4	18		T8	18
valid_sources[0x5a]	572927	1			T1	7		T2	70		T4	17
valid_sources[0x5b]	560970	1			T1	2		T2	103		T4	18
valid_sources[0x5c]	557045	1			T1	3		T2	105		T4	14
valid_sources[0x5d]	1910227	1			T2	86		T4	16		T8	29
valid_sources[0x5e]	549799	1			T1	6		T2	21		T4	9
valid_sources[0x5f]	551477	1			T1	4		T2	171		T4	7
valid_sources[0x60]	549926	1			T1	2		T2	39		T4	22
valid_sources[0x61]	1397309	1			T1	10		T2	13		T4	19
valid_sources[0x62]	578611	1			T2	82		T4	14		T8	13
valid_sources[0x63]	703188	1			T2	47		T4	16		T8	23
valid_sources[0x64]	1456597	1			T2	65		T4	15		T8	22
valid_sources[0x65]	549084	1			T2	18		T4	18		T8	22
valid_sources[0x66]	614058	1			T2	68		T4	14		T8	23
valid_sources[0x67]	558305	1			T2	30		T4	18		T8	23
valid_sources[0x68]	551788	1			T2	35		T4	17		T8	16
valid_sources[0x69]	590034	1			T2	24		T4	14		T8	19
valid_sources[0x6a]	555393	1			T1	3		T2	20		T4	20
valid_sources[0x6b]	532091	1			T2	36		T4	15		T8	22
valid_sources[0x6c]	756263	1			T1	1		T2	63		T4	12
valid_sources[0x6d]	574185	1			T2	29		T4	17		T8	21
valid_sources[0x6e]	587089	1			T2	37		T4	13		T8	20
valid_sources[0x6f]	638474	1			T1	11		T2	19		T4	11
valid_sources[0x70]	1475581	1			T1	7		T2	21		T4	16
valid_sources[0x71]	539539	1			T2	120		T4	13		T8	26
valid_sources[0x72]	618602	1			T2	55		T4	15		T8	22
valid_sources[0x73]	567226	1			T1	1		T2	54		T4	10
valid_sources[0x74]	543458	1			T1	2		T2	49		T4	22
valid_sources[0x75]	559644	1			T2	12		T4	8		T8	30
valid_sources[0x76]	605276	1			T2	18		T4	10		T8	16
valid_sources[0x77]	570831	1			T2	38		T4	19		T8	27
valid_sources[0x78]	1245226	1			T2	5		T4	17		T8	25
valid_sources[0x79]	540401	1			T2	78		T4	22		T8	22
valid_sources[0x7a]	624068	1			T2	42		T4	14		T8	17
valid_sources[0x7b]	625122	1			T2	76		T4	16		T8	22
valid_sources[0x7c]	560336	1			T1	5		T2	40		T4	16
valid_sources[0x7d]	550589	1			T2	2		T4	14		T8	20
valid_sources[0x7e]	572562	1			T1	4		T2	16		T4	20
valid_sources[0x7f]	542404	1			T2	79		T4	15		T8	28
valid_sources[0x80]	559014	1			T1	10		T2	33		T4	17

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

73725856

1

T1

39

T2

5666

T3

2291

values[0x0]

all_enables

biggest_size

38161844

1

T1

16

T2

2811

T3

1161

values[0x1]

all_enables

biggest_size

38160937

1

T1

18

T2

2937

T3

1162

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42560	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

152302

1

T2

1

T3

1

T4

1812

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53572	1			T4	523		T8	881		T29	620
values[0x0]	68315	1			T1	1		T2	3		T3	1
values[0x1]	72975	1			T4	775		T8	1373		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32756	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

162106

1

T2

1

T3

1

T4

1884

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1082	1			T4	10		T29	11		T68	6
valid_sources[0x01]	785	1			T4	4		T29	7		T84	8
valid_sources[0x02]	988	1			T4	5		T29	6		T68	6
valid_sources[0x03]	992	1			T4	5		T8	154		T29	7
valid_sources[0x04]	642	1			T4	5		T29	3		T84	7
valid_sources[0x05]	758	1			T4	6		T12	1		T29	6
valid_sources[0x06]	612	1			T4	9		T8	1		T29	7
valid_sources[0x07]	782	1			T4	3		T29	12		T68	1
valid_sources[0x08]	638	1			T4	9		T29	11		T84	8
valid_sources[0x09]	1027	1			T4	9		T29	7		T84	7
valid_sources[0x0a]	656	1			T4	4		T12	1		T29	13
valid_sources[0x0b]	666	1			T4	4		T29	11		T84	19
valid_sources[0x0c]	720	1			T4	12		T8	2		T12	1
valid_sources[0x0d]	1030	1			T4	6		T29	7		T68	12
valid_sources[0x0e]	779	1			T4	11		T12	2		T29	9
valid_sources[0x0f]	587	1			T4	9		T29	9		T68	1
valid_sources[0x10]	926	1			T4	4		T29	12		T84	10
valid_sources[0x11]	740	1			T4	10		T29	6		T84	11
valid_sources[0x12]	630	1			T4	2		T12	1		T29	4
valid_sources[0x13]	573	1			T4	4		T29	6		T68	21
valid_sources[0x14]	513	1			T4	2		T29	10		T68	2
valid_sources[0x15]	735	1			T4	3		T8	1		T29	8
valid_sources[0x16]	874	1			T4	7		T8	182		T29	11
valid_sources[0x17]	618	1			T4	7		T8	1		T29	8
valid_sources[0x18]	693	1			T4	10		T29	7		T68	6
valid_sources[0x19]	834	1			T4	11		T29	9		T68	3
valid_sources[0x1a]	609	1			T4	7		T29	9		T68	7
valid_sources[0x1b]	674	1			T4	8		T29	11		T68	10
valid_sources[0x1c]	662	1			T4	4		T29	8		T84	13
valid_sources[0x1d]	853	1			T4	6		T29	7		T68	7
valid_sources[0x1e]	717	1			T4	8		T29	6		T68	16
valid_sources[0x1f]	994	1			T4	6		T8	116		T29	11
valid_sources[0x20]	727	1			T4	5		T12	1		T29	6
valid_sources[0x21]	1086	1			T4	11		T8	140		T29	3
valid_sources[0x22]	942	1			T4	10		T11	1		T29	7
valid_sources[0x23]	1197	1			T4	4		T12	1		T29	12
valid_sources[0x24]	798	1			T4	12		T29	12		T68	11
valid_sources[0x25]	702	1			T4	6		T8	1		T12	1
valid_sources[0x26]	605	1			T4	14		T8	9		T12	1
valid_sources[0x27]	828	1			T4	12		T8	10		T29	11
valid_sources[0x28]	594	1			T4	20		T29	9		T84	11
valid_sources[0x29]	943	1			T4	9		T29	6		T84	9
valid_sources[0x2a]	645	1			T4	10		T29	13		T68	8
valid_sources[0x2b]	688	1			T4	8		T29	3		T84	7
valid_sources[0x2c]	759	1			T4	2		T8	1		T29	9
valid_sources[0x2d]	903	1			T3	1		T4	12		T29	5
valid_sources[0x2e]	689	1			T4	6		T29	10		T68	2
valid_sources[0x2f]	601	1			T4	5		T12	1		T29	4
valid_sources[0x30]	645	1			T4	9		T8	1		T12	1
valid_sources[0x31]	769	1			T4	10		T29	7		T84	13
valid_sources[0x32]	649	1			T4	3		T29	8		T68	5
valid_sources[0x33]	838	1			T4	14		T29	8		T84	7
valid_sources[0x34]	723	1			T4	10		T12	2		T29	13
valid_sources[0x35]	547	1			T4	4		T12	1		T29	8
valid_sources[0x36]	683	1			T4	6		T29	14		T34	1
valid_sources[0x37]	696	1			T4	6		T8	1		T29	9
valid_sources[0x38]	677	1			T4	8		T29	10		T20	1
valid_sources[0x39]	549	1			T4	9		T8	1		T29	13
valid_sources[0x3a]	1150	1			T4	12		T12	1		T29	7
valid_sources[0x3b]	695	1			T4	7		T29	9		T68	6
valid_sources[0x3c]	664	1			T4	5		T29	11		T84	12
valid_sources[0x3d]	666	1			T4	5		T29	6		T68	3
valid_sources[0x3e]	747	1			T4	12		T29	10		T84	11
valid_sources[0x3f]	609	1			T4	6		T29	8		T68	3
valid_sources[0x40]	890	1			T4	2		T8	169		T29	6
valid_sources[0x41]	773	1			T4	8		T12	1		T29	10
valid_sources[0x42]	728	1			T4	8		T29	11		T68	4
valid_sources[0x43]	731	1			T4	9		T8	3		T29	10
valid_sources[0x44]	691	1			T4	5		T29	14		T68	22
valid_sources[0x45]	706	1			T4	10		T29	10		T20	1
valid_sources[0x46]	829	1			T4	11		T8	1		T29	14
valid_sources[0x47]	893	1			T4	8		T29	7		T68	5
valid_sources[0x48]	752	1			T4	3		T29	11		T84	8
valid_sources[0x49]	664	1			T4	6		T29	9		T84	5
valid_sources[0x4a]	784	1			T4	9		T12	1		T29	5
valid_sources[0x4b]	593	1			T4	10		T29	12		T68	1
valid_sources[0x4c]	788	1			T4	9		T29	3		T84	8
valid_sources[0x4d]	648	1			T4	8		T29	7		T84	12
valid_sources[0x4e]	764	1			T4	4		T29	7		T68	2
valid_sources[0x4f]	1075	1			T4	8		T8	1		T12	2
valid_sources[0x50]	629	1			T4	8		T9	2		T29	4
valid_sources[0x51]	760	1			T4	6		T12	1		T29	8
valid_sources[0x52]	724	1			T4	6		T29	8		T68	4
valid_sources[0x53]	1241	1			T4	8		T29	17		T68	1
valid_sources[0x54]	755	1			T4	9		T29	11		T68	12
valid_sources[0x55]	658	1			T4	3		T29	12		T84	13
valid_sources[0x56]	679	1			T4	9		T29	11		T68	1
valid_sources[0x57]	1135	1			T4	11		T12	1		T29	6
valid_sources[0x58]	849	1			T4	5		T12	1		T29	9
valid_sources[0x59]	693	1			T4	6		T8	2		T29	12
valid_sources[0x5a]	991	1			T4	10		T8	1		T29	12
valid_sources[0x5b]	1030	1			T4	7		T29	7		T84	7
valid_sources[0x5c]	689	1			T4	8		T29	11		T84	4
valid_sources[0x5d]	816	1			T4	10		T12	1		T29	13
valid_sources[0x5e]	645	1			T4	7		T29	9		T68	12
valid_sources[0x5f]	918	1			T4	7		T8	123		T29	6
valid_sources[0x60]	755	1			T4	4		T29	17		T68	7
valid_sources[0x61]	705	1			T4	11		T10	2		T29	8
valid_sources[0x62]	809	1			T4	9		T29	9		T84	11
valid_sources[0x63]	701	1			T4	6		T29	6		T68	1
valid_sources[0x64]	664	1			T4	6		T8	1		T29	12
valid_sources[0x65]	604	1			T4	5		T8	34		T29	13
valid_sources[0x66]	711	1			T4	9		T12	1		T29	6
valid_sources[0x67]	1029	1			T4	9		T12	1		T29	6
valid_sources[0x68]	636	1			T4	7		T12	1		T30	1
valid_sources[0x69]	607	1			T4	11		T8	1		T29	12
valid_sources[0x6a]	792	1			T4	4		T29	13		T68	10
valid_sources[0x6b]	806	1			T4	9		T12	1		T29	11
valid_sources[0x6c]	530	1			T4	11		T29	10		T84	13
valid_sources[0x6d]	709	1			T4	3		T8	6		T29	10
valid_sources[0x6e]	743	1			T4	11		T29	7		T68	1
valid_sources[0x6f]	878	1			T4	12		T29	11		T68	11
valid_sources[0x70]	769	1			T4	4		T8	4		T29	11
valid_sources[0x71]	773	1			T4	6		T12	1		T29	8
valid_sources[0x72]	790	1			T4	5		T12	1		T29	15
valid_sources[0x73]	642	1			T4	9		T29	11		T68	20
valid_sources[0x74]	631	1			T4	9		T29	6		T68	4
valid_sources[0x75]	645	1			T4	14		T8	1		T29	9
valid_sources[0x76]	719	1			T4	10		T8	4		T29	9
valid_sources[0x77]	767	1			T4	7		T8	2		T29	4
valid_sources[0x78]	586	1			T4	6		T8	1		T29	9
valid_sources[0x79]	865	1			T4	9		T12	1		T29	8
valid_sources[0x7a]	760	1			T4	12		T29	11		T68	14
valid_sources[0x7b]	706	1			T4	9		T8	3		T29	14
valid_sources[0x7c]	551	1			T4	10		T12	1		T29	11
valid_sources[0x7d]	736	1			T4	6		T8	2		T12	2
valid_sources[0x7e]	647	1			T4	5		T29	9		T68	1
valid_sources[0x7f]	735	1			T4	11		T8	3		T13	11
valid_sources[0x80]	545	1			T4	3		T12	1		T29	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

41174

1

T4

478

T8

854

T29

560

values[0x0]

all_enables

biggest_size

56998

1

T2

1

T3

1

T4

642

values[0x1]

all_enables

biggest_size

54130

1

T4

692

T8

1294

T11

1