Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16582687

1

T1

358

T2

1173

T3

502

full_word

146963617

1

T1

73

T2

11414

T3

4614

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	163546054	1			T1	431		T2	12587		T3	5116
auto[TlIntgErrCmd]	83	1			T78	6		T79	6		T80	7
auto[TlIntgErrData]	83	1			T78	1		T79	1		T80	7
auto[TlIntgErrBoth]	84	1			T78	3		T79	3		T80	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

78843449

1

T1

243

T2

6253

T3

2536

auto[1]

84702855

1

T1

188

T2

6334

T3

2580

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8128802	1			T1	204		T2	587		T3	245
auto[TlIntgErrNone]	partial	auto[1]	8453652	1			T1	154		T2	586		T3	257
auto[TlIntgErrNone]	full_word	auto[0]	70714531	1			T1	39		T2	5666		T3	2291
auto[TlIntgErrNone]	full_word	auto[1]	76249069	1			T1	34		T2	5748		T3	2323
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T78	4		T79	2		T80	3
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T78	1		T79	3		T80	3
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T79	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T78	1		T80	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	39	1			T78	1		T79	1		T80	4
auto[TlIntgErrData]	partial	auto[1]	39	1			T80	2		T127	2		T128	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T130	1		T133	1		T135	1
auto[TlIntgErrData]	full_word	auto[1]	1	1			T80	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1			T78	2		T80	4		T127	2
auto[TlIntgErrBoth]	partial	auto[1]	45	1			T79	2		T80	2		T127	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T130	1		T131	1		T136	1
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T78	1		T79	1		T137	1