Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	776016	1			T1	3		T4	4		T31	4759
auto[1]	11674866	1			T1	5		T2	5267		T3	14
auto[2]	597045	1			T1	1		T4	2		T31	2490
auto[3]	11413779	1			T2	5348		T3	9		T4	2

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	15472246	1			T2	8812		T3	17		T4	6
auto[1]	2310588	1			T1	1		T2	859		T3	5
auto[2]	2346722	1			T2	857		T3	1		T4	1
auto[3]	4332150	1			T1	8		T2	87		T31	96

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10308500

1

T1

9

T2

10615

T3

23

auto[1]

14153206

1

T31

1

T48

60306

T74

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	310076	1			T4	3		T31	3925		T5	2
auto[0]	auto[0]	auto[1]	31802	1			T4	1		T31	410		T32	287
auto[0]	auto[0]	auto[2]	31477	1			T31	379		T32	284		T73	25
auto[0]	auto[0]	auto[3]	36724	1			T1	3		T31	44		T71	5
auto[0]	auto[1]	auto[0]	3801726	1			T2	4370		T3	10		T10	3030
auto[0]	auto[1]	auto[1]	390281	1			T1	1		T2	400		T3	4
auto[0]	auto[1]	auto[2]	403733	1			T2	452		T31	34		T49	681
auto[0]	auto[1]	auto[3]	297368	1			T1	4		T2	45		T31	19
auto[0]	auto[2]	auto[0]	224656	1			T4	2		T31	2097		T5	1
auto[0]	auto[2]	auto[1]	24228	1			T31	207		T32	188		T73	32
auto[0]	auto[2]	auto[2]	26023	1			T31	165		T5	1		T32	157
auto[0]	auto[2]	auto[3]	27903	1			T1	1		T31	21		T71	5
auto[0]	auto[3]	auto[0]	3649415	1			T2	4442		T3	7		T4	1
auto[0]	auto[3]	auto[1]	385746	1			T2	459		T3	1		T31	14
auto[0]	auto[3]	auto[2]	394016	1			T2	405		T3	1		T4	1
auto[0]	auto[3]	auto[3]	273326	1			T2	42		T31	12		T49	155
auto[1]	auto[0]	auto[0]	11940	1			T31	1		T48	550		T115	184
auto[1]	auto[0]	auto[1]	54714	1			T48	2539		T115	775		T118	2454
auto[1]	auto[0]	auto[2]	54546	1			T48	2654		T115	779		T118	2506
auto[1]	auto[0]	auto[3]	244737	1			T48	12027		T115	3262		T103	2
auto[1]	auto[1]	auto[0]	3733873	1			T48	90		T77	80331		T98	64016
auto[1]	auto[1]	auto[1]	704808	1			T48	2611		T77	7399		T98	5799
auto[1]	auto[1]	auto[2]	697206	1			T48	401		T77	8056		T98	6542
auto[1]	auto[1]	auto[3]	1645871	1			T48	11810		T77	725		T98	552
auto[1]	auto[2]	auto[0]	8522	1			T48	536		T118	504		T143	1143
auto[1]	auto[2]	auto[1]	39419	1			T48	2453		T118	2267		T143	5455
auto[1]	auto[2]	auto[2]	44770	1			T48	2087		T115	690		T118	1650
auto[1]	auto[2]	auto[3]	201524	1			T48	9894		T115	3013		T118	7520
auto[1]	auto[3]	auto[0]	3732038	1			T48	33		T74	1		T77	79945
auto[1]	auto[3]	auto[1]	679590	1			T48	217		T77	8122		T98	6324
auto[1]	auto[3]	auto[2]	694951	1			T48	2251		T77	7278		T98	5722
auto[1]	auto[3]	auto[3]	1604697	1			T48	10153		T76	1		T77	728