Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.90	100.00	88.89	100.00		100.00	70.59	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1073642021	218727	0	0
ctrl_regwen_rd_A	1073642021	5795	0	0
exec_rd_A	1073642021	5162	0	0
exec_regwen_rd_A	1073642021	5716	0	0
readback_rd_A	1073642021	3717	0	0
readback_regwen_rd_A	1073642021	3317	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	218727	0	0
T4	94455	3265	0	0
T8	103188	3751	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	5420	0	0
T30	75136	0	0	0
T33	0	5984	0	0
T54	0	6018	0	0
T59	0	5141	0	0
T68	23757	1002	0	0
T84	0	3764	0	0
T85	0	3933	0	0
T86	0	1127	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	5795	0	0
T8	103188	302	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	0	0	0
T30	75136	0	0	0
T34	33699	0	0	0
T59	0	382	0	0
T68	23757	0	0	0
T86	0	117	0	0
T120	0	284	0	0
T121	0	193	0	0
T122	0	390	0	0
T123	0	138	0	0
T124	0	124	0	0
T125	0	145	0	0
T126	0	210	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	5162	0	0
T8	103188	273	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	0	0	0
T30	75136	0	0	0
T34	33699	0	0	0
T59	0	335	0	0
T68	23757	0	0	0
T86	0	120	0	0
T120	0	247	0	0
T121	0	184	0	0
T122	0	285	0	0
T123	0	115	0	0
T124	0	114	0	0
T125	0	147	0	0
T126	0	245	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	5716	0	0
T8	103188	315	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	0	0	0
T30	75136	0	0	0
T34	33699	0	0	0
T59	0	305	0	0
T68	23757	0	0	0
T86	0	86	0	0
T120	0	268	0	0
T121	0	226	0	0
T122	0	417	0	0
T123	0	112	0	0
T124	0	132	0	0
T125	0	142	0	0
T126	0	221	0	0

readback_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	3717	0	0
T8	103188	328	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	0	0	0
T30	75136	0	0	0
T34	33699	0	0	0
T59	0	273	0	0
T68	23757	0	0	0
T86	0	102	0	0
T120	0	219	0	0
T121	0	168	0	0
T122	0	407	0	0
T123	0	78	0	0
T124	0	76	0	0
T125	0	122	0	0
T126	0	196	0	0

readback_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1073642021	3317	0	0
T8	103188	309	0	0
T9	74146	0	0	0
T10	72244	0	0	0
T11	539	0	0	0
T12	394884	0	0	0
T13	760428	0	0	0
T29	84997	0	0	0
T30	75136	0	0	0
T34	33699	0	0	0
T59	0	290	0	0
T68	23757	0	0	0
T86	0	74	0	0
T120	0	161	0	0
T121	0	145	0	0
T122	0	317	0	0
T123	0	137	0	0
T124	0	78	0	0
T125	0	135	0	0
T126	0	119	0	0