Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16123490	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159126695

1

T2

17660

T3

85137

T4

20921

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	86299556	1			T2	1969		T3	46967		T4	57074
values[0x0]	42870212	1			T2	7908		T3	22460		T4	19377
values[0x1]	46080417	1			T2	7783		T3	24251		T4	37217

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8202589	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167047596

1

T2

17660

T3

89416

T4

67068

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	529751	1			T2	93		T3	475		T4	383
valid_sources[0x01]	535430	1			T2	53		T3	448		T4	430
valid_sources[0x02]	570316	1			T2	20		T3	316		T4	328
valid_sources[0x03]	1340362	1			T2	110		T3	376		T4	430
valid_sources[0x04]	539344	1			T2	48		T3	361		T4	455
valid_sources[0x05]	617394	1			T2	89		T3	354		T4	467
valid_sources[0x06]	534075	1			T2	66		T3	336		T4	418
valid_sources[0x07]	616498	1			T2	83		T3	311		T4	401
valid_sources[0x08]	538121	1			T2	100		T3	379		T4	494
valid_sources[0x09]	768910	1			T2	33		T3	363		T4	431
valid_sources[0x0a]	584008	1			T2	167		T3	249		T4	420
valid_sources[0x0b]	600063	1			T2	109		T3	311		T4	494
valid_sources[0x0c]	571689	1			T2	67		T3	367		T4	372
valid_sources[0x0d]	634120	1			T2	62		T3	497		T4	471
valid_sources[0x0e]	545910	1			T2	63		T3	315		T4	425
valid_sources[0x0f]	605114	1			T2	37		T3	363		T4	543
valid_sources[0x10]	569427	1			T2	93		T3	338		T4	429
valid_sources[0x11]	775730	1			T2	129		T3	332		T4	477
valid_sources[0x12]	601905	1			T2	81		T3	313		T4	397
valid_sources[0x13]	551519	1			T2	24		T3	364		T4	351
valid_sources[0x14]	2006502	1			T2	68		T3	351		T4	488
valid_sources[0x15]	578193	1			T2	52		T3	395		T4	485
valid_sources[0x16]	785607	1			T2	64		T3	269		T4	601
valid_sources[0x17]	553032	1			T2	76		T3	437		T4	325
valid_sources[0x18]	530533	1			T2	121		T3	423		T4	475
valid_sources[0x19]	619947	1			T2	63		T3	347		T4	379
valid_sources[0x1a]	534970	1			T2	50		T3	377		T4	438
valid_sources[0x1b]	564323	1			T2	53		T3	314		T4	380
valid_sources[0x1c]	625730	1			T2	146		T3	364		T4	445
valid_sources[0x1d]	740198	1			T2	48		T3	457		T4	514
valid_sources[0x1e]	552373	1			T2	49		T3	388		T4	391
valid_sources[0x1f]	610558	1			T2	162		T3	462		T4	397
valid_sources[0x20]	1906338	1			T2	77		T3	328		T4	343
valid_sources[0x21]	558469	1			T2	62		T3	335		T4	385
valid_sources[0x22]	529262	1			T2	93		T3	447		T4	457
valid_sources[0x23]	562128	1			T2	81		T3	395		T4	434
valid_sources[0x24]	600323	1			T2	58		T3	329		T4	409
valid_sources[0x25]	563358	1			T2	100		T3	304		T4	365
valid_sources[0x26]	555911	1			T2	99		T3	287		T4	552
valid_sources[0x27]	576342	1			T2	81		T3	313		T4	488
valid_sources[0x28]	602613	1			T2	115		T3	306		T4	330
valid_sources[0x29]	583084	1			T2	90		T3	373		T4	379
valid_sources[0x2a]	598203	1			T2	68		T3	368		T4	422
valid_sources[0x2b]	578054	1			T2	66		T3	384		T4	467
valid_sources[0x2c]	560267	1			T2	53		T3	412		T4	440
valid_sources[0x2d]	546155	1			T2	111		T3	437		T4	357
valid_sources[0x2e]	1667163	1			T2	93		T3	328		T4	453
valid_sources[0x2f]	550179	1			T2	97		T3	389		T4	482
valid_sources[0x30]	2102001	1			T2	113		T3	352		T4	558
valid_sources[0x31]	552948	1			T2	102		T3	345		T4	456
valid_sources[0x32]	551388	1			T2	41		T3	335		T4	477
valid_sources[0x33]	555831	1			T2	62		T3	393		T4	452
valid_sources[0x34]	585501	1			T2	40		T3	387		T4	418
valid_sources[0x35]	551928	1			T2	112		T3	358		T4	454
valid_sources[0x36]	555102	1			T2	73		T3	396		T4	439
valid_sources[0x37]	638994	1			T2	60		T3	406		T4	498
valid_sources[0x38]	3376069	1			T2	65		T3	370		T4	433
valid_sources[0x39]	539610	1			T2	76		T3	432		T4	376
valid_sources[0x3a]	777150	1			T2	76		T3	380		T4	419
valid_sources[0x3b]	635461	1			T2	71		T3	376		T4	563
valid_sources[0x3c]	1663048	1			T2	43		T3	311		T4	352
valid_sources[0x3d]	556977	1			T2	65		T3	333		T4	461
valid_sources[0x3e]	567472	1			T2	65		T3	274		T4	404
valid_sources[0x3f]	550780	1			T2	83		T3	420		T4	430
valid_sources[0x40]	547330	1			T2	41		T3	527		T4	427
valid_sources[0x41]	1750117	1			T2	34		T3	358		T4	439
valid_sources[0x42]	746904	1			T2	51		T3	432		T4	390
valid_sources[0x43]	594144	1			T2	44		T3	354		T4	376
valid_sources[0x44]	635536	1			T2	51		T3	269		T4	548
valid_sources[0x45]	537986	1			T2	49		T3	355		T4	440
valid_sources[0x46]	558739	1			T2	103		T3	375		T4	279
valid_sources[0x47]	538450	1			T2	50		T3	319		T4	380
valid_sources[0x48]	619873	1			T2	73		T3	392		T4	424
valid_sources[0x49]	565439	1			T2	81		T3	419		T4	447
valid_sources[0x4a]	573983	1			T2	115		T3	358		T4	390
valid_sources[0x4b]	580578	1			T2	28		T3	355		T4	336
valid_sources[0x4c]	559462	1			T2	49		T3	351		T4	339
valid_sources[0x4d]	550173	1			T2	57		T3	346		T4	410
valid_sources[0x4e]	1013684	1			T2	98		T3	489		T4	492
valid_sources[0x4f]	559420	1			T2	104		T3	296		T4	441
valid_sources[0x50]	607475	1			T2	56		T3	362		T4	434
valid_sources[0x51]	559490	1			T2	33		T3	353		T4	564
valid_sources[0x52]	587807	1			T2	87		T3	310		T4	353
valid_sources[0x53]	565115	1			T2	29		T3	409		T4	470
valid_sources[0x54]	1842726	1			T2	36		T3	473		T4	360
valid_sources[0x55]	554320	1			T2	70		T3	355		T4	603
valid_sources[0x56]	542876	1			T2	77		T3	350		T4	419
valid_sources[0x57]	591823	1			T2	68		T3	376		T4	345
valid_sources[0x58]	561143	1			T2	72		T3	410		T4	414
valid_sources[0x59]	552764	1			T2	26		T3	380		T4	428
valid_sources[0x5a]	530133	1			T2	2		T3	334		T4	504
valid_sources[0x5b]	569651	1			T2	124		T3	389		T4	404
valid_sources[0x5c]	559732	1			T2	159		T3	410		T4	560
valid_sources[0x5d]	534093	1			T2	73		T3	322		T4	477
valid_sources[0x5e]	550153	1			T2	57		T3	326		T4	417
valid_sources[0x5f]	559501	1			T2	166		T3	322		T4	578
valid_sources[0x60]	554520	1			T2	66		T3	397		T4	431
valid_sources[0x61]	590308	1			T2	40		T3	413		T4	401
valid_sources[0x62]	548280	1			T2	41		T3	479		T4	470
valid_sources[0x63]	543031	1			T2	87		T3	315		T4	477
valid_sources[0x64]	575447	1			T2	37		T3	379		T4	476
valid_sources[0x65]	533733	1			T2	46		T3	414		T4	548
valid_sources[0x66]	552943	1			T2	79		T3	407		T4	432
valid_sources[0x67]	633995	1			T2	63		T3	282		T4	507
valid_sources[0x68]	546483	1			T2	27		T3	322		T4	353
valid_sources[0x69]	555858	1			T2	53		T3	427		T4	641
valid_sources[0x6a]	544946	1			T2	81		T3	399		T4	469
valid_sources[0x6b]	549693	1			T2	115		T3	406		T4	538
valid_sources[0x6c]	567542	1			T2	33		T3	360		T4	414
valid_sources[0x6d]	562105	1			T2	43		T3	280		T4	555
valid_sources[0x6e]	525913	1			T2	68		T3	415		T4	370
valid_sources[0x6f]	644666	1			T2	85		T3	358		T4	416
valid_sources[0x70]	539539	1			T2	46		T3	371		T4	480
valid_sources[0x71]	604585	1			T2	93		T3	404		T4	391
valid_sources[0x72]	569307	1			T2	39		T3	367		T4	411
valid_sources[0x73]	592935	1			T2	72		T3	377		T4	406
valid_sources[0x74]	539448	1			T2	98		T3	287		T4	426
valid_sources[0x75]	535340	1			T2	31		T3	468		T4	383
valid_sources[0x76]	591153	1			T2	55		T3	321		T4	505
valid_sources[0x77]	540449	1			T2	39		T3	322		T4	457
valid_sources[0x78]	527700	1			T2	42		T3	364		T4	525
valid_sources[0x79]	574789	1			T2	90		T3	461		T4	409
valid_sources[0x7a]	526535	1			T2	136		T3	277		T4	479
valid_sources[0x7b]	593927	1			T2	100		T3	457		T4	409
valid_sources[0x7c]	539459	1			T2	82		T3	483		T4	404
valid_sources[0x7d]	540162	1			T2	89		T3	390		T4	448
valid_sources[0x7e]	562698	1			T2	47		T3	313		T4	378
valid_sources[0x7f]	616381	1			T2	59		T3	282		T4	500
valid_sources[0x80]	574492	1			T2	58		T3	385		T4	402

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78195666

1

T2

1969

T3

42643

T4

10451

values[0x0]

all_enables

biggest_size

40465307

1

T2

7908

T3

21162

T4

5296

values[0x1]

all_enables

biggest_size

40465722

1

T2

7783

T3

21332

T4

5174

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43276	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

138287

1

T2

4238

T3

13

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	50303	1			T2	1238		T3	9		T27	259
values[0x0]	63391	1			T2	1563		T3	20		T4	3
values[0x1]	67869	1			T1	1		T2	1727		T3	17

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33746	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

147817

1

T2

4392

T3

14

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	895	1			T2	23		T5	3		T27	2
valid_sources[0x01]	594	1			T2	46		T5	2		T27	3
valid_sources[0x02]	634	1			T2	17		T27	3		T6	4
valid_sources[0x03]	556	1			T2	8		T27	3		T29	9
valid_sources[0x04]	842	1			T2	6		T5	1		T27	3
valid_sources[0x05]	639	1			T2	11		T27	1		T56	1
valid_sources[0x06]	757	1			T2	17		T27	6		T29	9
valid_sources[0x07]	670	1			T2	14		T29	11		T17	3
valid_sources[0x08]	672	1			T2	9		T56	1		T29	9
valid_sources[0x09]	893	1			T2	1		T5	1		T27	4
valid_sources[0x0a]	505	1			T2	60		T27	1		T7	4
valid_sources[0x0b]	707	1			T2	55		T5	2		T27	4
valid_sources[0x0c]	615	1			T2	6		T3	1		T5	1
valid_sources[0x0d]	706	1			T2	27		T29	8		T142	2
valid_sources[0x0e]	753	1			T2	20		T3	1		T5	1
valid_sources[0x0f]	797	1			T2	2		T5	2		T27	3
valid_sources[0x10]	802	1			T2	20		T3	2		T27	5
valid_sources[0x11]	723	1			T2	13		T27	6		T29	8
valid_sources[0x12]	705	1			T2	8		T5	1		T27	3
valid_sources[0x13]	566	1			T2	5		T5	2		T27	1
valid_sources[0x14]	555	1			T2	45		T5	1		T29	5
valid_sources[0x15]	725	1			T2	10		T5	1		T27	5
valid_sources[0x16]	624	1			T2	20		T3	2		T27	4
valid_sources[0x17]	956	1			T2	18		T5	1		T27	4
valid_sources[0x18]	808	1			T2	19		T6	2		T29	10
valid_sources[0x19]	497	1			T2	2		T27	6		T29	14
valid_sources[0x1a]	649	1			T2	15		T7	1		T56	1
valid_sources[0x1b]	659	1			T45	2		T29	10		T38	9
valid_sources[0x1c]	1029	1			T2	16		T5	2		T27	3
valid_sources[0x1d]	550	1			T2	15		T5	1		T11	2
valid_sources[0x1e]	501	1			T2	13		T5	1		T27	1
valid_sources[0x1f]	616	1			T2	11		T3	1		T5	1
valid_sources[0x20]	937	1			T2	42		T29	9		T38	8
valid_sources[0x21]	971	1			T2	15		T5	1		T27	2
valid_sources[0x22]	582	1			T2	12		T27	4		T7	1
valid_sources[0x23]	901	1			T2	22		T27	2		T7	1
valid_sources[0x24]	811	1			T2	25		T3	1		T27	6
valid_sources[0x25]	675	1			T2	1		T3	1		T27	1
valid_sources[0x26]	575	1			T2	7		T20	1		T56	3
valid_sources[0x27]	728	1			T5	3		T27	3		T20	5
valid_sources[0x28]	862	1			T2	32		T5	1		T27	1
valid_sources[0x29]	811	1			T2	13		T3	2		T5	2
valid_sources[0x2a]	618	1			T2	23		T27	4		T29	9
valid_sources[0x2b]	765	1			T2	44		T3	1		T5	2
valid_sources[0x2c]	637	1			T2	18		T5	7		T27	8
valid_sources[0x2d]	665	1			T2	22		T5	3		T27	12
valid_sources[0x2e]	741	1			T2	33		T5	1		T7	4
valid_sources[0x2f]	866	1			T2	7		T27	9		T6	6
valid_sources[0x30]	824	1			T2	18		T27	2		T45	1
valid_sources[0x31]	536	1			T2	1		T20	1		T45	2
valid_sources[0x32]	589	1			T2	5		T27	6		T21	1
valid_sources[0x33]	757	1			T2	37		T6	6		T7	2
valid_sources[0x34]	459	1			T2	9		T5	1		T27	6
valid_sources[0x35]	479	1			T2	7		T5	2		T27	8
valid_sources[0x36]	737	1			T2	56		T5	1		T27	7
valid_sources[0x37]	575	1			T2	23		T3	1		T4	2
valid_sources[0x38]	521	1			T2	1		T5	2		T20	2
valid_sources[0x39]	1130	1			T2	12		T3	1		T5	1
valid_sources[0x3a]	620	1			T2	9		T5	1		T20	4
valid_sources[0x3b]	625	1			T2	5		T3	1		T27	3
valid_sources[0x3c]	787	1			T2	12		T3	1		T4	1
valid_sources[0x3d]	901	1			T2	6		T45	4		T7	1
valid_sources[0x3e]	670	1			T2	13		T3	1		T5	1
valid_sources[0x3f]	682	1			T2	8		T5	3		T27	11
valid_sources[0x40]	549	1			T2	3		T3	1		T27	7
valid_sources[0x41]	1139	1			T2	9		T3	1		T5	3
valid_sources[0x42]	469	1			T2	18		T5	1		T27	1
valid_sources[0x43]	710	1			T27	1		T29	23		T38	15
valid_sources[0x44]	550	1			T2	24		T5	2		T27	2
valid_sources[0x45]	579	1			T2	7		T5	2		T27	1
valid_sources[0x46]	495	1			T2	1		T3	1		T27	3
valid_sources[0x47]	693	1			T5	1		T27	5		T6	4
valid_sources[0x48]	681	1			T2	31		T27	5		T45	2
valid_sources[0x49]	710	1			T2	1		T5	1		T27	1
valid_sources[0x4a]	545	1			T5	1		T7	1		T56	1
valid_sources[0x4b]	675	1			T2	23		T29	12		T57	4
valid_sources[0x4c]	666	1			T2	2		T27	1		T29	4
valid_sources[0x4d]	1160	1			T2	11		T5	2		T27	11
valid_sources[0x4e]	884	1			T2	12		T29	14		T57	7
valid_sources[0x4f]	736	1			T2	31		T5	1		T27	2
valid_sources[0x50]	697	1			T5	2		T27	3		T56	1
valid_sources[0x51]	723	1			T2	13		T5	3		T27	2
valid_sources[0x52]	627	1			T2	30		T3	1		T5	1
valid_sources[0x53]	511	1			T2	6		T5	1		T27	8
valid_sources[0x54]	936	1			T2	9		T5	1		T27	4
valid_sources[0x55]	710	1			T2	12		T5	2		T27	3
valid_sources[0x56]	536	1			T2	20		T29	6		T38	11
valid_sources[0x57]	768	1			T2	17		T3	1		T5	2
valid_sources[0x58]	660	1			T2	49		T27	3		T56	1
valid_sources[0x59]	788	1			T2	50		T5	3		T27	8
valid_sources[0x5a]	684	1			T2	32		T5	2		T20	2
valid_sources[0x5b]	704	1			T2	23		T5	3		T27	3
valid_sources[0x5c]	860	1			T2	10		T5	1		T27	1
valid_sources[0x5d]	657	1			T2	4		T27	2		T20	3
valid_sources[0x5e]	801	1			T2	23		T5	4		T27	2
valid_sources[0x5f]	492	1			T2	4		T5	1		T27	3
valid_sources[0x60]	745	1			T2	31		T3	1		T5	1
valid_sources[0x61]	952	1			T2	20		T5	3		T27	7
valid_sources[0x62]	627	1			T2	6		T27	1		T6	1
valid_sources[0x63]	565	1			T2	31		T5	1		T9	1
valid_sources[0x64]	592	1			T3	1		T27	9		T44	1
valid_sources[0x65]	613	1			T2	32		T5	1		T27	4
valid_sources[0x66]	593	1			T2	21		T27	2		T29	7
valid_sources[0x67]	958	1			T2	9		T5	1		T27	1
valid_sources[0x68]	642	1			T2	15		T27	3		T29	9
valid_sources[0x69]	735	1			T2	82		T5	2		T27	5
valid_sources[0x6a]	672	1			T2	32		T3	1		T5	3
valid_sources[0x6b]	684	1			T2	48		T5	1		T27	2
valid_sources[0x6c]	666	1			T2	9		T5	1		T29	11
valid_sources[0x6d]	524	1			T2	29		T56	1		T29	14
valid_sources[0x6e]	722	1			T2	39		T4	1		T5	2
valid_sources[0x6f]	866	1			T2	28		T3	1		T5	2
valid_sources[0x70]	569	1			T2	8		T27	4		T29	7
valid_sources[0x71]	598	1			T2	34		T5	1		T27	8
valid_sources[0x72]	767	1			T2	35		T3	1		T27	1
valid_sources[0x73]	647	1			T2	26		T27	3		T56	3
valid_sources[0x74]	727	1			T2	5		T5	1		T27	3
valid_sources[0x75]	914	1			T2	29		T13	2		T56	2
valid_sources[0x76]	659	1			T2	32		T7	3		T29	10
valid_sources[0x77]	573	1			T2	6		T3	1		T5	1
valid_sources[0x78]	892	1			T2	5		T27	6		T29	13
valid_sources[0x79]	942	1			T27	4		T20	1		T7	1
valid_sources[0x7a]	755	1			T2	10		T3	1		T5	3
valid_sources[0x7b]	533	1			T5	2		T27	1		T29	13
valid_sources[0x7c]	611	1			T2	17		T27	1		T29	8
valid_sources[0x7d]	752	1			T2	31		T5	2		T27	2
valid_sources[0x7e]	957	1			T2	40		T5	1		T27	4
valid_sources[0x7f]	693	1			T2	3		T5	1		T27	9
valid_sources[0x80]	668	1			T2	9		T5	1		T27	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

37566

1

T2

1141

T3

5

T27

235

values[0x0]

all_enables

biggest_size

51739

1

T2

1547

T3

6

T4

1

values[0x1]

all_enables

biggest_size

48982

1

T2

1550

T3

2

T5

23