Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16019548

1

T2

6547

T3

7595

T4

92747

full_word

156082010

1

T2

18454

T3

75930

T4

20921

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	172101258	1			T2	25001		T3	83525		T4	113668
auto[TlIntgErrCmd]	97	1			T66	2		T67	4		T68	1
auto[TlIntgErrData]	98	1			T66	6		T67	1		T68	4
auto[TlIntgErrBoth]	105	1			T66	2		T67	5		T68	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

83070703

1

T2

3507

T3

36814

T4

57074

auto[1]

89030855

1

T2

21494

T3

46711

T4

56594

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7846715	1			T2	1334		T3	3378		T4	46623
auto[TlIntgErrNone]	partial	auto[1]	8172567	1			T2	5213		T3	4217		T4	46124
auto[TlIntgErrNone]	full_word	auto[0]	75223853	1			T2	2173		T3	33436		T4	10451
auto[TlIntgErrNone]	full_word	auto[1]	80858123	1			T2	16281		T3	42494		T4	10470
auto[TlIntgErrCmd]	partial	auto[0]	42	1			T66	1		T67	2		T68	1
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T67	2		T119	2		T126	4
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T119	1		T122	1		T128	2
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T66	1		T119	1		-	-
auto[TlIntgErrData]	partial	auto[0]	45	1			T66	4		T67	1		T68	1
auto[TlIntgErrData]	partial	auto[1]	46	1			T66	2		T68	3		T119	2
auto[TlIntgErrData]	full_word	auto[0]	2	1			T129	1		T130	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T129	1		T123	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1			T67	1		T68	2		T119	2
auto[TlIntgErrBoth]	partial	auto[1]	54	1			T66	2		T67	3		T68	3
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T67	1		T129	4		T123	1
auto[TlIntgErrBoth]	full_word	auto[1]	11	1			T129	2		T122	1		T131	2